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ZWang142's avatar
ZWang142
Icon for New Contributor rankNew Contributor
6 years ago

1/2.5/5/10G Multi-rate Ethernet PHY simulation cannot reach rx_block_lock

The simulation of the example design, provided by the "Low Latency Ethernet 10G MAC" IP, is running fine. However, when simulating my design, the PHY can not acheive rx_block_lock. The waveform sho...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Interesting.

refclk_10g is used in 3 IP. I made below design changes but Modelsim run still failed.

  • Can you let me know what's the exact changes that you made ?

Below is the modification steps

  • Generate Eth 10G MAC + MultiratePHY with default refclk 644MHz
  • Then change refclk from 644MHz to 322MHz for below 3 IP and regenerate the IP
    • Multirate PHY, ATX_PLL 10G, core_fPLL
  • Modify test bench (tb_top.sv) refclk_10g from 644MHz to 322MHz
  • Modify certain IP design files name as the IP has been regenerated (modelsim_files.tcl) in \simulation\ed_sim\setup_scripts\common

Thanks.

Regards,

dlim

ZWang142's avatar
ZWang142
Icon for New Contributor rankNew Contributor
6 years ago

Forgot to mention: you have to copy the mif files from the newly generated PHY, to the rtl/reconfig folder of the example design...