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ZWang142's avatar
ZWang142
Icon for New Contributor rankNew Contributor
5 years ago

1/2.5/5/10G Multi-rate Ethernet PHY simulation cannot reach rx_block_lock

The simulation of the example design, provided by the "Low Latency Ethernet 10G MAC" IP, is running fine. However, when simulating my design, the PHY can not acheive rx_block_lock. The waveform sho...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,

Thanks for the clarification.

rx_pma_clkout is derived from rx_cdr_refclk_1. If you have provided correct clock frequency in test bench file then by right rx_pma_clkout should be 156.25MHz.

  • I need to understand your design better and try to duplicate issue from my side.

Can you share with me more info as below ?

  1. Which FPGA product that you are using ? Is it Stratix 10 ? Can you share with me your FPGA part number ?
  2. Which Quartus version that you are using ? Have you tried with latest Quartus version like Quartus Pro v20.1 ?
  3. Which simulator tool and what version that you are using ? Make sure you are using the corresponding simulator tool that pair with its Quartus version
  4. Do you had a chance to try out other simulator tool to see of the issue still persist ?
  5. Lastly, can you share with me your Multirate-PHY IP setting screenshot ?

Thanks.

Regards,

dlim

ZWang142's avatar
ZWang142
Icon for New Contributor rankNew Contributor
5 years ago

0. My rx_cdr_refclk_1 is 322.265 Mhz.

1- Stratix 10, 1SM16BEU2F55E2VG

2- Quartus Pro v20.1

3- VCS 2017

4- I tried Modelsim 10.6 on Windows but it failed to handle long file names. The testbench files provided by the example design have very long file names.

5- Please see the attached