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ZWang142
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5 years ago

1/2.5/5/10G Multi-rate Ethernet PHY simulation cannot reach rx_block_lock

The simulation of the example design, provided by the "Low Latency Ethernet 10G MAC" IP, is running fine. However, when simulating my design, the PHY can not acheive rx_block_lock. The waveform sho...
ZWang142's avatar
ZWang142
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5 years ago

More info: in my waveform,

rx_cdr_refclk_1 is 322.265625 MHz, as specified by the Reference clock frequency for 10 GbE (MHz) parameter.

However,

rx_pma_clkout is only 78 MHz (it should be 156.25 MHz according to the spec).

  • ZWang142's avatar
    ZWang142
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    5 years ago

    BTW, the warning has been solved. I copied tb_top.sv from the example design, where the refclk_10g is 644 Mhz, while in my design, it should be 322 Mhz. After changing refclk_10g to 322 Mhz, the warning is gone. But rx_pma_clkout is 78 Mhz...