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ZWang142's avatar
ZWang142
Icon for New Contributor rankNew Contributor
5 years ago

1/2.5/5/10G Multi-rate Ethernet PHY simulation cannot reach rx_block_lock

The simulation of the example design, provided by the "Low Latency Ethernet 10G MAC" IP, is running fine. However, when simulating my design, the PHY can not acheive rx_block_lock. The waveform sho...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,

Thanks for the clarification.

rx_pma_clkout is derived from rx_cdr_refclk_1. If you have provided correct clock frequency in test bench file then by right rx_pma_clkout should be 156.25MHz.

  • I need to understand your design better and try to duplicate issue from my side.

Can you share with me more info as below ?

  1. Which FPGA product that you are using ? Is it Stratix 10 ? Can you share with me your FPGA part number ?
  2. Which Quartus version that you are using ? Have you tried with latest Quartus version like Quartus Pro v20.1 ?
  3. Which simulator tool and what version that you are using ? Make sure you are using the corresponding simulator tool that pair with its Quartus version
  4. Do you had a chance to try out other simulator tool to see of the issue still persist ?
  5. Lastly, can you share with me your Multirate-PHY IP setting screenshot ?

Thanks.

Regards,

dlim

ZWang142's avatar
ZWang142
Icon for New Contributor rankNew Contributor
5 years ago

In the example design, I changed the refclk to 322 MHz:

  • Changed IP settings for the PHY and generated HDL for both syn and sim
  • Changed IP settings for the 10g PLL and genreated HDL
  • Changed refclk_10g in tb_top to 322 MHz
  • Generated simulation scripts using Quartus
  • Changed other simulation scripts so VCS can compile

Now, in the example design, rx_pma_clkout becomes 78 MHz and it cannot achive rx_block_lock.

Would you please try 322 MHz for the "alt_em10g32_0_EXAMPLE_DESIGN/LL10G_1G_2_5G_10G" example design?

Thanks.

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