Why do i get this error when I use lvds?

Hello Aqid,

Thanks for you reply this post.

This issue happened just as I made one simple project for LVDS test and trying. Now we try internal PLL, instead of external PLL, the LVDS function looks fine.

As you mentioned to try clock input, as following images, we already try this to receiver external ADC output.

However, here i have another question about LVDS need you help. Which is of LVDS constrain. We know that LVDS needs input termination and with the value of "Differential", as above image. We applied this constrain for ADC output pairs. They run well.

So we have another type LVDS pairs input, which are not from external ADC chips. They come from comparator devices output. FPGA use differential I/O pairs to receiver them. When we apply same constrain as ADC output pairs, they can't run well. The comparator output run as pulse signal, we can use Signaltap to monitor its signal quality. It's very bad under this constrain.

But they can run well when On-Chip Termination for Transceiver Rx pin (with 100 ohms value)constrains were applied to them. My question is what's the different between them?

Hi Aqid,

Yes, you're right. The tranceiver termination settings are ignored.

If this is the case, the differential pairs interconnection have no termination configurations. How to ensure the circuit run well?

I check C10GX datasheet, lvds vid only have min requirement as 100mV. So I have the the external input signal swing range. The comparator output doesn't drive to FPGA directly. Compartors otuput drive OR gate firstly, then OR gates outputs drive to FPGA's lvds receivers. The OR gates otuput signals are CML pairs. We use DC coupling, so they connected directly. The OR gate output signal swing is much higher enough than FPGA lvds VID requirement, 100mV, as following imgae:

The OR gate output signal was measured as following,

So we think we may apply fpga interanl termination for lvds receiver.

Hi,

1. The bottom blue line signal is just of the oscilloscope's reference to trace the object pulse.

2. You're right, I check the hardware again. The connection between OR gate's CML output and FPGA lvds receiver input under AC coupling. In this case, we still have above issue. That's we can't enable the on-chip termination.

Do we nned other extra outside pull-up and/or pull-down resistors?

Thanks

Hi Aqid,

Thanks for you info above. There are two things which need to confirm with you.

1. Your provided example is of external LVPECL drives FPGA LVPECL I/O. You know, our case is of external CML drives FPGA LVDS I/O. Can we use the same structure of the example in our case?

2. If item 1's answer is "Yes". According to your comments "Then the two 50 Ohm resistors serve as the DC bias connection and 100 Ohm differential termination", after using this structure, the LVDS receiver's inside differential OCT should not need to be used any more?

Thanks

Hello Aqid,

Thanks for you information.

Can you give me the link for Stratix II? I have Stratix II device datasheet long time ago. I checked this datasheet, however, I couldn't fine the similar information as your above link of Cyclone 10 GX device.

Thnaks

Best Regard

Hi Aqid,

I have this datasheet in my computer, however, I can't find the example as Cyclone 10 GX which you provided previously. As following image:

Are sure the similar examples can be found in Stratix II datasheet?

Thanks

Best Regard

Hi FvM,

Thanks for you follow this post.

1. The primary problem of this post is that I can't apply "on-chip differential termination" constrain for my LVDS receiver. Becasue the receiver output signal will be distorted. The input CML signal is received by FPGA's LVDS receiver. It's single bit pulse signal. We need this pulse signal in our following logic design. This pulse signal will be hided in mass noise when "n-chip differential termination" constrain is used. So we went to use tranceiver Rx pin constrain. And the pulse could be recognized after that. But Aqid told me that this constrain should be ignored by Quartus. He's right, we have check the compilation report carefuly. So in this case, we could recognize this pulse without any on-chip constrain.

2. The CML differential signal outputed from OR gate logic chip. So it should be of data stream. This sinlge bit signal just gather random pulse signal. FPGA logic need to receive and reconize it correctly.

3. Our hardware engineer have already reserved AC/DC coupling and outside pull up/down resistor options. We can switch to select what option we want.

4. If outside AC coupling used, Aqid give me above examples of LVPECL TO LVPECL in Cyclone 10 GX. And also he said if I want to refer similar example of LVDS receiver, i can check and refer from Stratix II datasheet. Unfortunately, i can't fine this kind of example from Stratix II datasheet.

That's all of my problem. I hope that i explain clearly.

Thanks

Best Regard

Hi Aqid,

Sorry, I mis-understand you, I expected to search the example of LVDS. Now I get the LVPECL AC coupling termination example from Stratix II datasheet.

Thanks

Best Regard