Forum Discussion
Occasional ContributorWhy do i get this error when I use lvds?
Hi,
Yes, I found it in Volume 2, pages 4-18, from the link I provided earlier.
Let me know if you can't find it.
Regards,
Aqid
Regular ContributorIf transceiver termination settings are applied to GPIO pins configured as LVDS, the assignment should be ignored. Check the fitter reports to confirm. There should be an ignored assignments (or I/O assignment warnings) report, and you can look at the input pins report to see which, if any, input termination is used.
Assuming the assignment is ignored and there is no input termination on the LVDS pins used for the comparator, then my guess is the signal has a low voltage swing. When termination is enabled, it will reduce the voltage swing, so if the swing is already low, enabling termination may reduce the VID too much for the receiver to operate properly.
Occasional ContributorHi Aqid,
Yes, you're right. The tranceiver termination settings are ignored.
If this is the case, the differential pairs interconnection have no termination configurations. How to ensure the circuit run well?
I check C10GX datasheet, lvds vid only have min requirement as 100mV. So I have the the external input signal swing range. The comparator output doesn't drive to FPGA directly. Compartors otuput drive OR gate firstly, then OR gates outputs drive to FPGA's lvds receivers. The OR gates otuput signals are CML pairs. We use DC coupling, so they connected directly. The OR gate output signal swing is much higher enough than FPGA lvds VID requirement, 100mV, as following imgae:
The OR gate output signal was measured as following,
So we think we may apply fpga interanl termination for lvds receiver.
