Occasional ContributorHi,
Yes, I found it in Volume 2, pages 4-18, from the link I provided earlier.
Let me know if you can't find it.
Regards,
Aqid
Super ContributorHi,
would you mind to specify the actual problem clearly? As far as I understand it's about CML received by Cyclone 10 GX? Do you need DC coupling (input signal is not DC-free, e.g. unencoded data stream) or not? What's the signal source, CML level specifications of devices are slightly different.
Whats's the relation to Stratix II?
Occasional ContributorHi FvM,
Thanks for you follow this post.
1. The primary problem of this post is that I can't apply "on-chip differential termination" constrain for my LVDS receiver. Becasue the receiver output signal will be distorted. The input CML signal is received by FPGA's LVDS receiver. It's single bit pulse signal. We need this pulse signal in our following logic design. This pulse signal will be hided in mass noise when "n-chip differential termination" constrain is used. So we went to use tranceiver Rx pin constrain. And the pulse could be recognized after that. But Aqid told me that this constrain should be ignored by Quartus. He's right, we have check the compilation report carefuly. So in this case, we could recognize this pulse without any on-chip constrain.
2. The CML differential signal outputed from OR gate logic chip. So it should be of data stream. This sinlge bit signal just gather random pulse signal. FPGA logic need to receive and reconize it correctly.
3. Our hardware engineer have already reserved AC/DC coupling and outside pull up/down resistor options. We can switch to select what option we want.
4. If outside AC coupling used, Aqid give me above examples of LVPECL TO LVPECL in Cyclone 10 GX. And also he said if I want to refer similar example of LVDS receiver, i can check and refer from Stratix II datasheet. Unfortunately, i can't fine this kind of example from Stratix II datasheet.
That's all of my problem. I hope that i explain clearly.
Thanks
Best Regard
