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New ContributorSDRAM ( Single Data Rate ) refresh verilog
Salve, sono nuovo nel forum e spero di non violare nessuna regola. Avrei bisogno di un consiglio.
Ho creato un modulo controller sdram in verilog per fpga EP4CE6F17I7N e sdram Hynix H57V2562GTR-75C compatibile con Micron MT48LC64M4A2. Il modulo è semplicissimo deve solo scrivere un valore in riga 0, colonna 0, eseguire un ciclo di refresh ( 8192 comandi di refresh, NOP tra i comandi di refresh, diciamo 8200 per assicurare che la riga 1 venga rinfrescata ) leggere il valore e inviarlo via seriale, in modo sequnziale, nessun comando viene inviato alla sdram durante il refresh. Il test funziona ma solo se il ciclo di refresh non è completo, ovvero, la riga 1 viene rinfrescata una sola volta. Il clock della FSM e della SDRAM sono entrambe 10MHz ( ALT_PLL, clock originale 50MHz ) per facilitare il debug con strumenti esterni ( analizzatore di segnali, oscilloscopio ), il clock sdram è sfasato di 90° rispetto al clock della FSM, il che consente alla sdram di campionare, sul fronte di salita del clock i comandi in modo corretto ( setup/hold ). Tuttavia anche con una procedura di refresh che sembra corretta il dato degrada... Sto ancora analizzando la cosa, tuttavia, anche con l'aiuto dell'IA non si riesce a trovare il problema, sembra tutto ok... Grazie.
4 Replies
AdzimZM_AlteraRegular Contributor
Hi
Is there any IP that you used and which Quartus version?
Regards,
Adzim
DarkSideOfTheSignalHi Adzim, thanks for the reply.
No i didn't use any "module" by Altera like Avalon for example, only the PLL module generated by Quartus II 13.0.1 Web Edition, more recent Quartus version, the last for example, on windows 11 has a graphical problem in the MegaWizard tool window, but this is another thing.
I simply asked the IA to generate a prototype controller for SDRAM, because it is the first time i have to use them, and now i know JEDEC, the way that sdram work... So i simply followed the timing characteristics, for the AUTO REFRESH command, needed by the sdram, considering the clock speed from the PLL and the relative period 1/F, and "adjusted" the controller, it can write, read ( burts 1 byte, on any bank )
May be i have to better evaluate metastability, the datasheet, or do some research and try understand what is going wrong... Neither the IA, after many try and after read some datasheet has found the problem. Today, i tryed to adapting another contoller from the git of the board, if this implementation work, i can evaluate all the signal and try to "mimic" it.
But for now i really doesn't understand wath is the cause of the refresh problem.
Best regards.- AdzimZM_Altera
Looks like you have managed to slowly resolve the issue.
I'm not sure how I can help you on this issue but I think you can also try a simulation run based on SDRAM IP design and observe the waveform.
Maybe you can get more idea based on that.
- DarkSideOfTheSignal
In reality the controller work.
The refresh is working. I found some erorrs in the .qsf ( pin definition ) file.
So becaouse the project is big ( 1 CPU 6502 in fpga work + ROM M9K work + RAM M9K work+ Micro SD controller work, SDRAM conotrolle in dev + VGA character mode with 6502 "kernal" driving work + VGA graphic mode single or, i'm not sure single back buffer or double back buffer, sprite engine, tile engine in progress, multi DMA channel in progress, buffer for write read the sdram in progress ecc ) i'm busy and may be i have created some problem accidentaly :) .
It's not a remake of MISTER but it's a complete console or "PC" so i'm very busy.
When possible i will publish the basic sdram ( sinchronous dynamic ram ) with no burst. Single write, single read, refresh... Thanks for your help.
This is the board i use if i can:
EP4CE6F17I7
Kit di sviluppo FPGA ALTERA Cyclone IV EP4CE6 Scheda PCB FPGA Altera EP4CE NIOSII e downloader USB Blaster - AliExpress 7
EP4CE10F17C8 + STM32F407
Scheda di sviluppo FPGA EP4CE6/EP4CE10+STM32F407 con Ethernet per algoritmi di immagine FSMC - AliExpress 502
