Forum Discussion
New ContributorSDRAM ( Single Data Rate ) refresh verilog
Regular Contributor
Looks like you have managed to slowly resolve the issue.
I'm not sure how I can help you on this issue but I think you can also try a simulation run based on SDRAM IP design and observe the waveform.
Maybe you can get more idea based on that.
New ContributorIn reality the controller work.
The refresh is working. I found some erorrs in the .qsf ( pin definition ) file.
So becaouse the project is big ( 1 CPU 6502 in fpga work + ROM M9K work + RAM M9K work+ Micro SD controller work, SDRAM conotrolle in dev + VGA character mode with 6502 "kernal" driving work + VGA graphic mode single or, i'm not sure single back buffer or double back buffer, sprite engine, tile engine in progress, multi DMA channel in progress, buffer for write read the sdram in progress ecc ) i'm busy and may be i have created some problem accidentaly :) .
It's not a remake of MISTER but it's a complete console or "PC" so i'm very busy.
When possible i will publish the basic sdram ( sinchronous dynamic ram ) with no burst. Single write, single read, refresh... Thanks for your help.
This is the board i use if i can:
EP4CE6F17I7
Kit di sviluppo FPGA ALTERA Cyclone IV EP4CE6 Scheda PCB FPGA Altera EP4CE NIOSII e downloader USB Blaster - AliExpress 7
EP4CE10F17C8 + STM32F407
Scheda di sviluppo FPGA EP4CE6/EP4CE10+STM32F407 con Ethernet per algoritmi di immagine FSMC - AliExpress 502
