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MinzhiWang
Occasional Contributor
Occasional ContributorWhy do i get this error when I use lvds?
Hello guys, My device is 10CX220YF780E5G and the Quartus is QPP23.4. I implemented one channel LVDS receiver in my project. External PLL was checked. After full complilation, I found LVDS module was...
Hi,
Yes, I found it in Volume 2, pages 4-18, from the link I provided earlier.
Let me know if you can't find it.
Regards,
Aqid
AqidAyman_Altera
Regular Contributor
Regular ContributorHi,
- Yes, the example for LVPECL is applicable to any AC coupled interface to the GPIO and dedicated clock input pins. This is just one circuit example, there are other ways to do it. Some customers use a 5 resistor solution which has a pull up and pull down on each of the p and n legs, then a 100 Ohm differential termination. You can find that example in the Stratix II handbook. The example from the Cyclone 10 GX handbook is an implied 4 resistor solution where Vicm is created with a voltage divider. If you happen to have a 1.2V or 1.25V supply on the board, you wouldn’t need the voltage divider resistors and then it would just be a 2 resistor solution (the two 50 Ohm resistors).
- Correct, when implementing these external biasing schemes, you would not use on-chip differential termination.
Hope this info helps to clarify you. Thanks.
MinzhiWangHello Aqid,
Thanks for you information.
Can you give me the link for Stratix II? I have Stratix II device datasheet long time ago. I checked this datasheet, however, I couldn't fine the similar information as your above link of Cyclone 10 GX device.
Thnaks
Best Regard
