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MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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Why do i get this error when I use lvds?

Hello guys, My device is 10CX220YF780E5G and the Quartus is QPP23.4. I implemented one channel LVDS receiver in my project. External PLL was checked. After full complilation, I found LVDS module was...
Generic Io
  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    1 year ago

    Hi,


    Yes, I found it in Volume 2, pages 4-18, from the link I provided earlier.

    Let me know if you can't find it.


    Regards,

    Aqid


AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

What is the significance of the blue trace in the scope shot?

Although we agree the Vid min is satisfied, we can’t tell the common mode voltage of the differential signal. It must also be in the supported common mode range of the Cyclone 10 GX LVDS receiver. There is mention of Voh on the CML datasheet indicating it is near VCC which is either 2.5V or 3.3V, so this is above our common mode range.

MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi,

1. The bottom blue line signal is just of the oscilloscope's reference to trace the object pulse.

2. You're right, I check the hardware again. The connection between OR gate's CML output and FPGA lvds receiver input under AC coupling. In this case, we still have above issue. That's we can't enable the on-chip termination.

Do we nned other extra outside pull-up and/or pull-down resistors?

Thanks