Occasional ContributorHi,
Yes, I found it in Volume 2, pages 4-18, from the link I provided earlier.
Let me know if you can't find it.
Regards,
Aqid
Regular ContributorHello,
Can you try to change the pin assigned for the dedicated clock input to be in the same bank as the LVDS channel pin?
Kindly confirm back if this suggestion is working or not.
Thanks.
Occasional ContributorHello Aqid,
Thanks for you reply this post.
This issue happened just as I made one simple project for LVDS test and trying. Now we try internal PLL, instead of external PLL, the LVDS function looks fine.
As you mentioned to try clock input, as following images, we already try this to receiver external ADC output.
However, here i have another question about LVDS need you help. Which is of LVDS constrain. We know that LVDS needs input termination and with the value of "Differential", as above image. We applied this constrain for ADC output pairs. They run well.
So we have another type LVDS pairs input, which are not from external ADC chips. They come from comparator devices output. FPGA use differential I/O pairs to receiver them. When we apply same constrain as ADC output pairs, they can't run well. The comparator output run as pulse signal, we can use Signaltap to monitor its signal quality. It's very bad under this constrain.
But they can run well when On-Chip Termination for Transceiver Rx pin (with 100 ohms value)constrains were applied to them. My question is what's the different between them?
