Help me in translation of VHDL to verilog

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Hello!

How can i convert a two-dimentional output & input port of vhdl into a verilog.

vhdl:

type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32;

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one input port varaarayin is declared as a type of VARIABLEARRAY.

& one output port vararrayout is also declared as a type of VARIABLEARRAY.

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I need a equivalent code for this because verilog didnt support 2-D array as input or output port.am i correct?

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Hi,

can you explain what you mean with a 2-D Array input/output ?

GPK

@GKP,

I am explaining with the help of example.

e.g.

variablearray is array (1 to nbrvarible_ct+10 ) of slv32;

the equivalent memory space occupy by this 2-D array in terms of 1-D array

is...

var1[(NBRVARIBLE_CT+10)*32:0] ;//here var1 is the array of (NBRVARIBLE_CT+10) locations & the each location of this array is of 32 bit wide..

I hope this is the proper explaination for you.

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@GKP,

I am explaining with the help of example.

e.g.

variablearray is array (1 to nbrvarible_ct+10 ) of slv32;

the equivalent memory space occupy by this 2-D array in terms of 1-D array

is...

var1[(NBRVARIBLE_CT+10)*32:0] ;//here var1 is the array of (NBRVARIBLE_CT+10) locations & the each location of this array is of 32 bit wide..

I hope this is the proper explaination for you.

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Hi,

you would like to define a memory ?

reg [7:0] mem [15:0] // defines a 16x8 memory , Data width 16 bit, Address width 8bit

Kind regards

GPK

Hi,

Dear GKP,

exectly same thing as you wrote.but i think,we cant declare the port variable like that // reg [7:0] mem [15:0] // as 2-D array.in verilog.

can you suggest me some alternative for that..

Regards,

Manoj

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Hi,

Dear GKP,

exectly same thing as you wrote.but i think,we cant declare the port variable like that // reg [7:0] mem [15:0] // as 2-D array.in verilog.

can you suggest me some alternative for that..

Regards,

Manoj

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Now I'm a little bit confused. Are talking about input or output port of a module ?

Kind regards

GPK

Hi,

I need to have used the variables as both input & output port. some variable as input port other as a output port..

Regards,

Manoj

You are correct that Verilog does not support arrays in input and output ports.

You will need need to either define vectors as input and outputs and assign them to a 2D array inside your module i.e. flatten the 2D array to a vector for i/o to the module.

or I believe System Verilog would do what you want

@vernmid,

Thanks for valuable reply.

You are correct.but i am having restriction to use of verilog only.

i did the same thing as you suggested,flatten the 2-D array in my module,

but main problem is the dependency of my module on various module also,

so should they people also have to modify their modules?

Regards,

Manoj

If the other modules in your system need to interface to your internal 2D array and are written in Verilog then yes they will also need to flatten the array to/from the ports as you have done.

All languages have restrictions and unlucky for you that you found one of the Verilog ones :confused:

Hope this has helped

ya thats ture.

thanks for clearing my doubt.

I am having one more doubt i have declared one port as inout.

so in verilog ideally it should be wire.

but I am assigning some value to same port inside the always block.

so for that perpose.it should be a reg only. so it is showing the error msg:port mode is incompatible with declaration.

so please suggest me some alternative for above problem

Regards,

Manoj