Help me in translation of VHDL to verilog

ya thats ture.

thanks for clearing my doubt.

I am having one more doubt i have declared one port as inout.

so in verilog ideally it should be wire.

but I am assigning some value to same port inside the always block.

so for that perpose.it should be a reg only. so it is showing the error msg:port mode is incompatible with declaration.

so please suggest me some alternative for above problem

Regards,

Manoj