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Honored Contributor

17 years ago

Help me in translation of VHDL to verilog

Hello! How can i convert a two-dimentional output & input port of vhdl into a verilog. vhdl: type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32; ----------------------------...

Altera_Forum

Honored Contributor

17 years ago

If the other modules in your system need to interface to your internal 2D array and are written in Verilog then yes they will also need to flatten the array to/from the ports as you have done.

All languages have restrictions and unlucky for you that you found one of the Verilog ones :confused:

Hope this has helped

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Help me in translation of VHDL to verilog

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