Help me in translation of VHDL to verilog

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Hello!

How can i convert a two-dimentional output & input port of vhdl into a verilog.

vhdl:

type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32;

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one input port varaarayin is declared as a type of VARIABLEARRAY.

& one output port vararrayout is also declared as a type of VARIABLEARRAY.

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I need a equivalent code for this because verilog didnt support 2-D array as input or output port.am i correct?

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Hi,

can you explain what you mean with a 2-D Array input/output ?

GPK