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Altera_Forum
Honored Contributor
Honored ContributorHelp me in translation of VHDL to verilog
Hello! How can i convert a two-dimentional output & input port of vhdl into a verilog. vhdl: type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32; ----------------------------...
Altera_ForumHonored Contributor
Honored ContributorHi,
I need to have used the variables as both input & output port. some variable as input port other as a output port.. Regards, Manoj
