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Altera_Forum
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17 years ago

Help me in translation of VHDL to verilog

Hello! How can i convert a two-dimentional output & input port of vhdl into a verilog. vhdl: type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32; ----------------------------...
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Altera_Forum
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17 years ago

@vernmid,

Thanks for valuable reply.

You are correct.but i am having restriction to use of verilog only.

i did the same thing as you suggested,flatten the 2-D array in my module,

but main problem is the dependency of my module on various module also,

so should they people also have to modify their modules?

Regards,

Manoj