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Altera_Forum
Honored Contributor
Honored ContributorHelp me in translation of VHDL to verilog
Hello! How can i convert a two-dimentional output & input port of vhdl into a verilog. vhdl: type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32; ----------------------------...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi, Dear GKP, exectly same thing as you wrote.but i think,we cant declare the port variable like that // reg [7:0] mem [15:0] // as 2-D array.in verilog. can you suggest me some alternative for that.. Regards, Manoj --- Quote End --- Now I'm a little bit confused. Are talking about input or output port of a module ? Kind regards GPK
