Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHelp me in translation of VHDL to verilog
Hello! How can i convert a two-dimentional output & input port of vhdl into a verilog. vhdl: type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32; ----------------------------...
Altera_ForumHonored Contributor
Honored ContributorYou are correct that Verilog does not support arrays in input and output ports.
You will need need to either define vectors as input and outputs and assign them to a 2D array inside your module i.e. flatten the 2D array to a vector for i/o to the module. or I believe System Verilog would do what you want
