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Altera_Forum
Honored Contributor
Honored ContributorHelp me in translation of VHDL to verilog
Hello! How can i convert a two-dimentional output & input port of vhdl into a verilog. vhdl: type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32; ----------------------------...
Altera_ForumHonored Contributor
Honored Contributor@GKP,
I am explaining with the help of example. e.g. variablearray is array (1 to nbrvarible_ct+10 ) of slv32; the equivalent memory space occupy by this 2-D array in terms of 1-D array is... var1[(NBRVARIBLE_CT+10)*32:0] ;//here var1 is the array of (NBRVARIBLE_CT+10) locations & the each location of this array is of 32 bit wide.. I hope this is the proper explaination for you.
