Help me in translation of VHDL to verilog

@GKP,

I am explaining with the help of example.

e.g.

variablearray is array (1 to nbrvarible_ct+10 ) of slv32;

the equivalent memory space occupy by this 2-D array in terms of 1-D array

is...

var1[(NBRVARIBLE_CT+10)*32:0] ;//here var1 is the array of (NBRVARIBLE_CT+10) locations & the each location of this array is of 32 bit wide..

I hope this is the proper explaination for you.