Altera_Forum
Honored Contributor
10 years agoEstimate total computation time in FPGA
Hi,
I am using MAX 10 FPGA to implement a controller for my power supply. The VHDL code for the controller is as follows. In this code the input 'I' is a pulse which helps to sample input Iref at a specific instant. The code is executed properly and behaves according to my expectation. Now, I would like to find what will be the total computation time from the moment Iref sample is captured to the moment Vab is calculated as shown below. I used Modelsim to judge the computation delay in a simple multiplication (for example,Ip1 calculation as shown below) or division(for example,Ip calculation as shown below) but could not see any delay. Kindly give some advice how I can find the computation delay for each operation below? entity Feedforwardv1 is Port ( Iref : in unsigned(15 downto 0); I : in STD_LOGIC; Vab : out signed(19 downto 0)); end Feedforwardv1; architecture Behavioral of Feedforwardv1 is signal Irefprev,Ii1,Irefs : integer := 0; signal Ii2,Ip,Ip1,Iis,Ii : integer := 0; signal Ii3,Ii3prev: integer := 0; signal Kpz : integer := 245; signal Kiz1 : integer := 37941; signal Kiz2 : integer := 1190; begin Ip1 <= Kpz*Irefs; Ip <= Ip1/4096; Ii1 <= Irefs - Irefprev; Ii2 <= Kiz1*Ii1; Iis <= Ii3prev+Ii2; Ii <= Iis/2048; Ii3 <= Kiz2*Ii; Vab <= to_signed((Ip+Ii),20); Process(I) begin if(rising_edge(I)) then Irefprev <= Irefs; Irefs <= to_integer(Iref); Ii3prev <= Ii3; --Vab <= to_signed((Ip+Ii),20); end if; end process; end Behavioral;