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Altera_Forum
Honored Contributor
Honored ContributorEstimate total computation time in FPGA
Hi, I am using MAX 10 FPGA to implement a controller for my power supply. The VHDL code for the controller is as follows. In this code the input 'I' is a pulse which helps to sample input Iref at ...
Altera_ForumHonored Contributor
Honored ContributorDivision will be a much greater delay.
Without compiling the circuit and looking in timequest, you will have no idea of the delay.
