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Altera_Forum
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10 years ago

Estimate total computation time in FPGA

Hi, I am using MAX 10 FPGA to implement a controller for my power supply. The VHDL code for the controller is as follows. In this code the input 'I' is a pulse which helps to sample input Iref at ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

You get a negative slack report when you don't have a Synopsys Design Constraints File(.sdc file) that describes the timing requirements. Quartus II then assumes a clock of 1 GHz (1 ns period) which obviously is never met.