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Altera_Forum
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10 years ago

Estimate total computation time in FPGA

Hi, I am using MAX 10 FPGA to implement a controller for my power supply. The VHDL code for the controller is as follows. In this code the input 'I' is a pulse which helps to sample input Iref at ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

I don't think that Tricky's (somewhat pedantic, although he is right in every point) answer won't be of much help ...

If your code simulates correctly, you can launch Quartus II and fit it in a real device. After compilation you can use Timequest to find the delay.

I estimate that it will be quite high but less than say 200 ns. Which would give you a 5 MHz update frequency.

I actually compiled you code and TimeQuest reported a tCO (clock to output) of 27 ns for a 10M08DAF484C8G device