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Altera_Forum
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10 years ago

Estimate total computation time in FPGA

Hi, I am using MAX 10 FPGA to implement a controller for my power supply. The VHDL code for the controller is as follows. In this code the input 'I' is a pulse which helps to sample input Iref at ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Hi Josyb,

I have included .sdc file in my project and have added a clock of clock period=20ns (50Hz) but still i have a negative slack. Despite this,my code works fine as what i see from my signals in logic analyser.

Also, I am now trying to estimate the propagation delay for my code by the number of operations in the calculation pipeline. Can you tell me what would be the delay of a single multiplication/division and a single addition in MAX 10 device.

If i know these numbers, i will be able to estimate the total delay.

Regards,

Misha