Estimate total computation time in FPGA

Modelsim will not show you the delay, because there is 0 delay in the HDL because you didnt model any. HDL code does not have any delay because it only models a circuit.

In the Max device, there will be a real delay, but because you have made an analogue circuit, this delay will vary depending on compilation routing, temperature, voltage and just random variations from chip to chip, so the delay is impossible to calculate.

If you used a synchronous circuit, you can work out the delay from the number of registers in the calculation pipeline.