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Honored Contributor
Honored ContributorEstimate total computation time in FPGA
Hi, I am using MAX 10 FPGA to implement a controller for my power supply. The VHDL code for the controller is as follows. In this code the input 'I' is a pulse which helps to sample input Iref at ...
Altera_ForumHonored Contributor
Honored ContributorWhat you want to say is:
although the input data is registered, the output value isn't. so the op has to realize that the transition after the i-pulse varies and probably will be a unstable (as not al bits will change at the same time) until the maximum delay given by timequest. To remedy this registering the output would be a good idea, but this comes with a penalty of one extra I-pulse delay. I agree this will need a different approach.
