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Altera_Forum
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10 years ago

Estimate total computation time in FPGA

Hi, I am using MAX 10 FPGA to implement a controller for my power supply. The VHDL code for the controller is as follows. In this code the input 'I' is a pulse which helps to sample input Iref at ...
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Altera_Forum
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10 years ago

Hi Tricky and Josyb,

Thank you both for replying. I am using 10M50DAF484C6GES. I am using a 50MHz (clock period=20ns ) clock. For me, if the total estimated delay from input to output is 200ns, it is good enough.

I also want to just estimate the delay and do not want an exact number for it. I am aware that the delay in the real implementation on FPGA will vary with voltage, temperature, routing, etc. I just wanted to learn how to estimate the delay for a particular code section.

Also, I wanted to know how i can use TimeQuest to judge the delays. Is the delay from clock to output (tCO), which means clock to Vab output (in my code) 27ns? After synthesizing my design,when i open TimeQuest and click on Report all summaries, it shows in the summary(setup) that i have a negative clock slack. How to fix this?

I am relatively new to FPGAs and QUARTUS II and do not know about all the tools but with the great support from Altera forums, I am learning fast.

Thank you again :)