New ContributorI was hoping to use LVDS serdes IP to implement acquisition system of 12 -bit ADC data using 2-wire LVDS:
However, this is not possible if only serialization factors of 4 and 8 are supported.
Is there a workaround or will this be supported in the future?
Super ContributorHi,
Agilex 3 and 5 SERDES are apparently limited to 4 and 8 deserialization factor. I'd assume for the time being that the restriction is in silicon and can't be overcome by software. See e.g. this previous discussion
Deserializers in Agilex 3 series | Altera Community - 324280
For x12 deserializer, I see an acceptable solution by using x4 deserializer, external 3x4 bit shift register and external PLL with FCLKx3 slow clock. Implementing e.g. x10 deserializer for popular 8b10b encoded links is more complicated, particularly when looking at synchronization logic. I'd appreciate an Altera reference design for 8b10b receiver with Agilex 3/5.
Regards Frank
Regular ContributorHi Lieven13
As far as I am aware, there is a workaround available where you can utilize LE to implement the data conversion, but it is for factor 7.
May I know if you have contacted any local FAEs for this?
Regards,
Aqid
New ContributorHi Aqid,
I have contacted local FAE for this a while ago. So far I did not receive any response.
I currently have the ADC interface implemented in logic using GPIO IP for DDR handling and this interface is working properly. I am able to fit 4 ADC's like this in FPGA, but then compiler starts complaining and I get fitting errors depending on the usage of signal tap signals and/or other logic that I need in my project. At this time I only need 2 ADCs so there is no big issue yet, but once I need to use all 4 ADCs on my board I will have a further look at this. One of the first things I will try is making use of the LVDS Serdes IP (factor of 4) what will result in 2x oversampling of the signals.
As Frank mentions it is a pitty that other (de)serialization factors seem to be forgotten on these new Agilex series as well as 8b/10b decoding.
Regards,
Lieven
Super ContributorHi Aqid,
deserialization factor of 5, 6, 7 or 10 is a common LVDS IO use case. To achieve it with Agilex 3/5 SERDES, parallel data need to be reassembled across word boundaries.
Presently, SERDES limitations of Agilex 3/5 and lack of ready-to-use soft IP supporting other deserialization factors is preventing wide usage of the new device series.
Regards
Frank
Super ContributorHi Lieven,
oversampling is a possible way to implement soft CDR, but it shouldn't be needed when receiving ADC data sent along with frame and bit clock. Here reassembly of SERDES output data to intended word length is the way to go. As stated above, it's straightforward for word lengths that are an integer multiple of SERDES output width like 12, more difficult for 10 or 14.
I presume there are reasons to simplify Agiles 3/5 SERDES block by stripping the variable length feature. I also expect that Altera product designers know FPGA use cases good enough to realize that other serialization factors than 4 and 8 are needed. So why not come up with respective IP or example code from the start?
Regards
Frank
