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Lieven13's avatar
Lieven13
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1 month ago

Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?

I was hoping to use LVDS serdes IP to implement acquisition system of 12 -bit ADC data using 2-wire LVDS:  However, this is not possible if only serialization factors of 4 and 8 are supported. ...
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AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 month ago

Hi Lieven13 

 

As far as I am aware, there is a workaround available where you can utilize LE to implement the data conversion, but it is for factor 7.

May I know if you have contacted any local FAEs for this?

 

Regards,
Aqid

  • Lieven13's avatar
    Lieven13
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    1 month ago

    Hi Aqid,

    I have contacted local FAE for this a while ago. So far I did not receive any response.

    I currently have the ADC interface implemented in logic using GPIO IP for DDR handling and this interface is working properly. I am able to fit 4 ADC's like this in FPGA, but then compiler starts complaining and I get fitting errors depending on the usage of signal tap signals  and/or other logic that I need in my project. At this time I only need 2 ADCs so there is no big issue yet, but once I need to use all 4 ADCs on my board I will have a further look at this. One of the first things I will try is making use of the LVDS Serdes IP (factor of 4) what will result in 2x oversampling of the signals.

    As Frank mentions it is a pitty that other (de)serialization factors seem to be forgotten on these new Agilex series as well as 8b/10b decoding.

    Regards,

    Lieven