Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?

Hi Lieven13​ ,

I didn't suggest oversampling. You'll sample 600 MBPS input data rate with 300 MHz DCLK. My above description was however assuming 12 Bit frames, I see now that it's 2x6 Bit. Respectively 2x4 Bit subframes have to be reassembled over two 100 MHz FCLK periods. 3x2x4 = 2x12 Bits. You need an external PLL that generates 150 MHz subframe clock along with 300 MHz DCLK.

Regards Frank