MAX 10 PLL Inverted Output Timing Inquiry

Hi, We are using a MAX 10 PLL in normal mode with an output phase shift of 180 degrees to drive the SCFIFO clock. What is the actual clock-to-clock phase relationship and propagation delay between the original pixel clock and the PLL-inverted output clock at the device pins?

More specifically, is the 180-degree phase shift ideal at the pin level, or should we expect additional PLL insertion delay, jitter, or phase error that must be accounted for in setup/hold timing?