Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?

Hi Lieven,

oversampling is a possible way to implement soft CDR, but it shouldn't be needed when receiving ADC data sent along with frame and bit clock. Here reassembly of SERDES output data to intended word length is the way to go. As stated above, it's straightforward for word lengths that are an integer multiple of SERDES output width like 12, more difficult for 10 or 14.

I presume there are reasons to simplify Agiles 3/5 SERDES block by stripping the variable length feature. I also expect that Altera product designers know FPGA use cases good enough to realize that other serialization factors than 4 and 8 are needed. So why not come up with respective IP or example code from the start?

Regards
Frank