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Altera_Forum
Honored Contributor
Honored ContributorEstimate total computation time in FPGA
Hi, I am using MAX 10 FPGA to implement a controller for my power supply. The VHDL code for the controller is as follows. In this code the input 'I' is a pulse which helps to sample input Iref at ...
Altera_ForumHonored Contributor
Honored ContributorThe problem is timequest will only give the worst case using the given model. The actual delay can (and probably will) vary in real time, and likely to be less than timequest actually estimates.
The only "safe" way to use logic like this, is to use a synchronous design.
