Altera_ForumHonored Contributor10 years agoEstimate total computation time in FPGA Hi, I am using MAX 10 FPGA to implement a controller for my power supply. The VHDL code for the controller is as follows. In this code the input 'I' is a pulse which helps to sample input Iref at ...Show More
Altera_ForumHonored Contributor10 years agowhere to look for this delay in timequest? In which report?
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