Detailed re-configurable PLL data description for Cyclone 10?

Hi,

Apologies,

1. PLL is sampling the serial-data on rising of scanclk.
2. PLL Component Scan Chain Order & Scan Chain Bit Order is given.
3. All 144 bits are addressed.

Please do refer below link.

https://www.intel.com/content/www/us/en/programmable/documentation/sxm1481253171919/pux1489734928671/wgw1489995238792.html

Let me know if need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

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At first sight, this looks like a transcript of the PDFs we already have.

The employee on this topic has a day off today, and yesterday was a holiday in this part of Germany. We'll take a closer look on Monday.

greetings,

Jens

Checking complete: It is the exact same info as in the datasheet. So no detailed bit order (which is no problem for us anymore as we got that from a different document combined with reverse-engineering the Quartus output).

No info how to calculate the charge pump or loop filter to get a specific bandwidth. So yet another *BUMP* with the kind request from a paying customer for proper documentation.

Just a hint: That order for 84 boxes=9996 pcs. 10CL010 is mine (placed through Arrow Germany). I really don't want to play around with "black box values" any longer, as we prefer engineering over tinkering here.

greetings,

Jens

Hi Jens,

Please refer to the attached .pdf file under table 2 that shows the 144 bits info for the Cyclone 10 LP PLL scan chain bitmap. We have been looking into this request internally and we require some time to check which documentation that has the 144 bits information. Even though the documentation stated Cyclone III, the PLL architecture for Cyclone 10 LP and Cyclone IV should be the same as Cyclone III. For details on the PLL Reconfig for Cyclone 10 LP, you can refer to the link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altpll_reconfig.pdf

Hopefully this might help to address your needs.

Regards,

Nooraini

Thanks for - well - again, nothing.

We've already been at the point where we checked Cyclone III documentation, because with such a long history of Altera-based FPGA designs, the similarity of Cyclone 10 vs. Cyclone III is more than obvious.

The document you've attached has errors. Table 2 uses the wrong order for LF_R_0 to LF_R_4 (bits 4 to 8). The table itself is tricky to read, as you need to send it to the PLL starting with bit 0, so you need to read the table from left to right, but from BOTTOM to TOP.

Needless to say that the document completely skips on the topic of filter settings: What are LF_R*, LF_C* and CP*, what do they do and how do you calculate them? The rest of the document is examples that don't correspond to our use case.

kind regards,

Jens

*BUMP*

Another week has passed, and still no documentation, not even a comment about the document errors I have reported here. Still trying to find that guy who has the knowledge?

kind regards,

Jens

Hi Jens,

Apologize for the delay. I believe you may already know that the LF_R*, LF_C* and CP is referring to loop filter resistor, loop filter capacitor and charge pump. However the information that you are asking specifically for your "case usage" (to calculate the charge pump or loop filter) is not available for public use. We've been checking the documentation and discussing internally back and forth regarding this inquiry with multiple different teams to end up with the same answers. All the information published in the Intel PLL documents are sufficient for users to be able to use the PLL IPs as it is without any issue. There no particular reason or justification for the engineering team to be releasing any other information than what has already been available/published in the official documents. Users can use Quartus PLL IP to get these M,N,C, LP, LF counter parameters either one of this method:

a) Set the Fref and Fout in ALTPLL IP and run Quartus compilation. After full compilation, user can see the information in Compilation Report->PLL Summary.

b) In the ALTPLL IP set the Fref and Fout settings in the PLL reconfiguration and select Generate a Configuration file in the ALTPLL MegaWizard Plug-In Manager. This will then generate either a .hex or .mif file with all the counter settings. Hence customer can use .hex or .mif file to set the ALTPLL_RECONFIG IP.

I apologize that this may not address to what you are looking for specifically, however the counters information can be be obtain without any issue (using the above methods). Thank you for your understanding.

Regards,

Nooraini

I was kind of expecting that you will retreat to a position that is like this. However, everyone who has been following this thread should know how silly it is to rate this information "classified", as I heard from the Arrow application engineers that there are other customers who have problems with the stability of these PLLs especially with low reference frequencies.

Please note that in a different design with a 10CL025, I've had trouble with the PLL running from an 8MHz reference clock; the PLL lost lock every now and then (maybe once every five seconds), despite perfect voltages and low ripple (<15mv) on 2.5V and 1.2V supplies. After I've put an extra 50MHz oscillator into the design and generated all clocks from that, all problems were gone. Note that jitter on the 8MHz clock was under 250ps - just in case the Arrow app engineers have not reported that case. The design was a migration from an EP3C25, where the 8MHz reference clock has worked for years in the field.

The 50MHz solution is not very satisfying, as I have bought FPGAs with PLLs that are supposed to work with reference clocks as low as 5MHz. In other words: Either the calculation(s) that these black-box-megafunctions do are not correct, or these PLLs just don't comply with the datasheets you're providing.

Having over 30 years of experience reading datasheets, I know that things sometimes need to be read "between the lines". I would have loved to calculate the loop filter components myself, as I'd have the chance to verify what's going wrong. After all, the errors in the document that was posted in this thread is showing without a doubt that people who work for Altera/Intel are not free of errors either.

Revealing a full description of these values can help improve the documentation of your products. I don't see how this could be any problem for Intel, other than admitting that you have no exact idea either (which is no problem, as it's not an Intel invention, but acquired from Altera). You should not be afraid of getting this right - it will ultimately improve your product.

kind regards,

Jens

Hi Jens,

I apologize that the responses here in the forum does not satisfy to what you are looking/requiring. We will channel your input and feedback to the internal/engineering team responsible on this IP for them to consider future documentation enhancement. You are correct there are errors in the document and what we can do is to submit the request to the internal team to take the appropriate action accordingly.

Nevertheless, regarding on the details information that your are questing, unless the engineering team can release/provide the information on the correct multiplication and divisor combination meeting the legal range/limits of the PLL/FPLL IP algorithm then we don't have the direct way to generate desire output clock without trial and error. The information that you are requesting are not available for public use since this is part of the IP and device proprietary.

For other PLL issues (Cyclone 10 PLL stability issue with low reference frequencies 8Mhz) than the original question posted here, I suggest that you can submit another thread. We will find and assign an engineer to help to look into it. Otherwise you may consult with your local distributor, Arrow if you still require further support on this topic.

Regards,

Nooraini

So I have a similar situation, where I'm trying to dynamically reconfigure a Cyclone IV PLL. If there were a small number of preset cases, then sure, using Quartus and compiling for each of the different cases, then hardcoding the results in software would be acceptable.

However in my case (as with the OPs) I have no preset cases, but require to work out workable (even if not ideal) LR/LC/ICP settings based on any required output frequency selected. Calculating the M/N values to acheive the clock rate is easy enough, but there is zero information on calculating the VCO loop filter parameters. Until you make it possible to run Quartus on a Nios processor, we're going to need a better way of calculating these parameters.

This is not rocket science, it should not be hard to give a table of values or some idea of how they are calculated. Nor do I see why it should be proprietary information.

Case and point, consider the Arria 10/Cyclone 10 GX devices, you literally give the information required in "AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices" - Table 5 on page 9 of that document gives a simple lookup table based on M value and desired bandwidth.

All we are asking for is the same information for the Cyclone 10 LP/Cyclone IV E devices. Is it really that difficult.

The PLL reconfiguration spreadsheet linked earlier in this discussion does not apply to this Cyclone IV devices - it seems to be for one of the Stratix devices with fractional PLLs, so even once you can view the hidden sheet with the little lookup table (seriously, why do people password protect excel files these days, it literally takes 1 second to unprotect them?), it's of no use as it's for a different device.

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The following is more for the OP and anyone else coming here with the same question than for the Intel folk - I'm sure they already nicely have this information tucked away in a virtual cupboard somewhere. Maybe lost when they rebranded Altera to Intel and again now they've decided to rebrand back again (great move by the way!?).

After a bit messing around with the ALTPLL megawizard trying different combinations, it seems as expected, the LP_R value is related to the M value (just as AN 728 shows for the 10 GX series, but with different value):

Note that I can't get M values higher than 253 out of the wizard due to the maximum VCO frequency of the Cyclone IV, so the list is incomplete.

As for the charge pump and loop filter capacitor values, regardless of what I select in the ALTPLL wizard, those are always 1 and 0 respectively. So apparently even the ALTPLL wizard which we are supposed to use doesn't even know how to calculate them!

In terms of bandwith Low/Medium/High, these seem to relate to the N value. The low bandwidth option seems to try to bump the N value as high as possible whist calculating the M/N ratio. The high bandwidth option seems to try and minimise the N value (most often it is set to 1). The medium bandwidth is most often the same as the high bandwidth, but occasionally has N value of 2 instead of 1. I presume it is something to do with the adjusting the PFD frequency, but haven't bothered looking into it as for now I'm just going to stick with minimising N.