Detailed re-configurable PLL data description for Cyclone 10?

So I have a similar situation, where I'm trying to dynamically reconfigure a Cyclone IV PLL. If there were a small number of preset cases, then sure, using Quartus and compiling for each of the different cases, then hardcoding the results in software would be acceptable.

However in my case (as with the OPs) I have no preset cases, but require to work out workable (even if not ideal) LR/LC/ICP settings based on any required output frequency selected. Calculating the M/N values to acheive the clock rate is easy enough, but there is zero information on calculating the VCO loop filter parameters. Until you make it possible to run Quartus on a Nios processor, we're going to need a better way of calculating these parameters.

This is not rocket science, it should not be hard to give a table of values or some idea of how they are calculated. Nor do I see why it should be proprietary information.

Case and point, consider the Arria 10/Cyclone 10 GX devices, you literally give the information required in "AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices" - Table 5 on page 9 of that document gives a simple lookup table based on M value and desired bandwidth.

All we are asking for is the same information for the Cyclone 10 LP/Cyclone IV E devices. Is it really that difficult.

The PLL reconfiguration spreadsheet linked earlier in this discussion does not apply to this Cyclone IV devices - it seems to be for one of the Stratix devices with fractional PLLs, so even once you can view the hidden sheet with the little lookup table (seriously, why do people password protect excel files these days, it literally takes 1 second to unprotect them?), it's of no use as it's for a different device.

-------

The following is more for the OP and anyone else coming here with the same question than for the Intel folk - I'm sure they already nicely have this information tucked away in a virtual cupboard somewhere. Maybe lost when they rebranded Altera to Intel and again now they've decided to rebrand back again (great move by the way!?).

After a bit messing around with the ALTPLL megawizard trying different combinations, it seems as expected, the LP_R value is related to the M value (just as AN 728 shows for the 10 GX series, but with different value):

Note that I can't get M values higher than 253 out of the wizard due to the maximum VCO frequency of the Cyclone IV, so the list is incomplete.

As for the charge pump and loop filter capacitor values, regardless of what I select in the ALTPLL wizard, those are always 1 and 0 respectively. So apparently even the ALTPLL wizard which we are supposed to use doesn't even know how to calculate them!

In terms of bandwith Low/Medium/High, these seem to relate to the N value. The low bandwidth option seems to try to bump the N value as high as possible whist calculating the M/N ratio. The high bandwidth option seems to try and minimise the N value (most often it is set to 1). The medium bandwidth is most often the same as the high bandwidth, but occasionally has N value of 2 instead of 1. I presume it is something to do with the adjusting the PFD frequency, but haven't bothered looking into it as for now I'm just going to stick with minimising N.