Detailed re-configurable PLL data description for Cyclone 10?

Thanks for - well - again, nothing.

We've already been at the point where we checked Cyclone III documentation, because with such a long history of Altera-based FPGA designs, the similarity of Cyclone 10 vs. Cyclone III is more than obvious.

The document you've attached has errors. Table 2 uses the wrong order for LF_R_0 to LF_R_4 (bits 4 to 8). The table itself is tricky to read, as you need to send it to the PLL starting with bit 0, so you need to read the table from left to right, but from BOTTOM to TOP.

Needless to say that the document completely skips on the topic of filter settings: What are LF_R*, LF_C* and CP*, what do they do and how do you calculate them? The rest of the document is examples that don't correspond to our use case.

kind regards,

Jens