Introducing OpenRDMA: An Open-Source 400G RDMA-Like SmartNIC Stack

Hello everyone,

I’m currently working on an open-source project called OpenRDMA, which focuses on developing a high-performance, FPGA-based 400G RDMA-like SmartNIC hardware and software stack. Since high-throughput open-source RDMA implementations are quite rare, we wanted to share our work with the community and get some feedback.

Here’s a quick overview of the project and its current technical specifications:

1. Target Architecture: Built from scratch to support 400G throughput networking interfaces.
2. Current Throughput: Achieved a stable ~200 Gbps in our hardware testbed, currently optimizing the pipeline for full 400G line rate.
3. Components Included: Complete FPGA RTL data path, hardware description files, and corresponding Linux host drivers.
4. Verification Workflow: Built using cocotb (Python). We also leveraged Large Language Models (LLMs) to co-generate python-based test scenarios, which significantly accelerated our edge-case bug hunting compared to traditional UVM.

The repository is fully open-source, and you can find it here: https://github.com/open-rdma/open-rdma

We are currently in the process of scaling the design to hit the full 400G throughput. I would highly appreciate any recommendations, insights, or experiences from those who have worked on similar high-bandwidth network engines or RoCE architectures on FPGAs. Specifically, any advice on pipeline optimization or managing timing closure at these data rates would be incredibly helpful.

Thanks in advance for your help and feedback!