Clarification on Agilex 3 W vs Y Device Variants and Security Feature Mapping
Hi support team, I hope you are doing well. I am currently evaluating Agilex™ 3 devices for a design and would like to clarify the detailed differences between the W and Y device variants, particularly regarding their security capabilities. After reviewing several official documents, I found that the description is not entirely aligned, and I would appreciate your clarification with references to the official definitions. I have mainly referred to the following documents: Security Overview for SDM-Based FPGA Devices Agilex™ 3 FPGAs and SoCs C‑Series Product Table Agilex™ 3 FPGAs and SoCs Device Data Sheet Questions and points needing clarification In the Agilex 3 product table, the W/Y/Z variants are differentiated by a “C-r-y-p-t-o” field. Could you please clarify: What exactly is included in “C-r-y-p-t-o”? Does this explicitly include: ECDSA authentication SHA‑384 integrity verification Secure boot / authenticated configuration Or does it also include lower-level cryptographic primitives (AES, SHA engines, etc.)? 2, In the Security Overview document, it states that: SDM contains cryptographic engines (AES, SHA, ECC) and key management hardware, and these can also be accessed by user logic. From this description, it appears that: Cryptographic primitives exist in the platform (even for Y devices) So the question is: Are cryptographic engines available in both Y and W variants? If yes, is the difference that: W enables secure system-level usage (authentication / secure boot) while Y only exposes these engines for user application use? 3,From the product table and security overview: PUF SPDM attestation Physical anti‑tamper monitoring appear to be available beyond just W variants. Could you confirm: Are these features available on both Y and W devices? If so, what is the functional difference in how they are used? For example: Monitoring vs enforcement Reporting vs blocking 4,In the document: Security Overview for SDM-Based FPGA Devices Table 1 seems to indicate that Agilex 3 devices generally support both encryption and authentication, without distinguishing between W and Y variants. This creates confusion when compared with the product table. Could you please clarify: Is Table 1 describing platform-level capability (architecture-based) rather than specific device configurations? And is the correct interpretation that: Only W variants enable full cryptographic security flows (e.g. authenticated configuration / root-of-trust) while Y variants provide only partial or application-level capabilities? My design really care the security and low power consumption rather than performance or high speed tranceivers. we only nee 30KLE, 300Kbit RAM, 2 PLL,200GPIO, no tranceiver ,no high speed needed so smaller density A3CY025BB18AI7S of Agilex3 might suitable but security W is not available in that small density, so I would like to know if we choose Code Y then what security features is missing from W. Regard JL
Verifying Cyclone V FPGA functionality using different FPGA flash devices (Intel / Micron).
We have two boards using the same Cyclone V FPGA, the only difference between the two boards is the serial flash devices for the FPGA, being the Micron or Intel flash device. We need to verify each of these flash device’s rpd file, to verify the FPGA functionality will be identical. However the rpd files are slightly different, from bytes 128 to 298 (ie: 170 bytes), as just below, and noting before and after this section it looks to be only padding, ie: FFs: So the question is, when validating the FPGA flash device’s rpd file (in software), is there a certain amount or section of initial bytes we can skip, though still ensure the exact same functionality of the FPGA itself ? Ie: I assume this first section of the rpd file does not affect the FPGA functionality (once flashed) ? Also would anyone know what is in the first section of the rpd file up to about byte 298 in this case ? Also noting I’m a software engineer with limited knowledge of the hardware, Thanks, Glenn
Inquiry regarding purchasing FPGA licenses
We are looking to purchase Intel FPGA software licenses for our company, specifically: * Intel NCO MegaCore IP license * Intel Quartus Prime Standard Edition license Can someone please help with the supplier on where we can do this transaction ? Thank you so much!
Does the 1SG280LU2F50E2VG support bitfile encryption
I am attempting to encrypt and load an image to the 1SG280LU2F50E2VG on our Stratix 10 GX development kit following the instructions in AN 970: Intel® Stratix® 10 Security Tutorial. When I attempt to download the "root.qky" to the FPGA I see: Info(209060): Started Programmer operation at Thu Feb 12 18:01:59 2026 Info(18942): Configuring device index 1 Info(18943): Configuration succeeded at device index 1 Info(20091): Programming public key on device 1 Error(209012): Operation failed Info(209061): Ended Programmer operation at Thu Feb 12 18:02:02 2026 Is the FPGA on the development kit compatible with encryption?
Arria 10 Reconfiguration
Hello, I am working with an Arria 10 (10AS048) and using an external FPGA to manage configuration from a flash memory. When working with a non encrypted image, i am able to configure, then reconfigure, without issue. When i try to do the same thing with an encrypted image i have success on the initial configuration. Once i try to reconfigure I never get config_done. The A10 never pulls nStatus low to indicate a CRC error. When encryption is used is there something in the A10 that is stopping reconfiguration? Thanks
