Verifying Cyclone V FPGA functionality using different FPGA flash devices (Intel / Micron).
We have two boards using the same Cyclone V FPGA, the only difference between the two boards is the serial flash devices for the FPGA, being the Micron or Intel flash device. We need to verify each of these flash device’s rpd file, to verify the FPGA functionality will be identical. However the rpd files are slightly different, from bytes 128 to 298 (ie: 170 bytes), as just below, and noting before and after this section it looks to be only padding, ie: FFs: So the question is, when validating the FPGA flash device’s rpd file (in software), is there a certain amount or section of initial bytes we can skip, though still ensure the exact same functionality of the FPGA itself ? Ie: I assume this first section of the rpd file does not affect the FPGA functionality (once flashed) ? Also would anyone know what is in the first section of the rpd file up to about byte 298 in this case ? Also noting I’m a software engineer with limited knowledge of the hardware, Thanks, Glenn27Views0likes2CommentsInquiry regarding purchasing FPGA licenses
We are looking to purchase Intel FPGA software licenses for our company, specifically: * Intel NCO MegaCore IP license * Intel Quartus Prime Standard Edition license Can someone please help with the supplier on where we can do this transaction ? Thank you so much!35Views0likes2CommentsDoes the 1SG280LU2F50E2VG support bitfile encryption
I am attempting to encrypt and load an image to the 1SG280LU2F50E2VG on our Stratix 10 GX development kit following the instructions in AN 970: Intel® Stratix® 10 Security Tutorial. When I attempt to download the "root.qky" to the FPGA I see: Info(209060): Started Programmer operation at Thu Feb 12 18:01:59 2026 Info(18942): Configuring device index 1 Info(18943): Configuration succeeded at device index 1 Info(20091): Programming public key on device 1 Error(209012): Operation failed Info(209061): Ended Programmer operation at Thu Feb 12 18:02:02 2026 Is the FPGA on the development kit compatible with encryption?20Views0likes3CommentsCyclone 10 LP Error Detection Timing
I am working with the cyclone 10 LP FPGA dev board from Altera. I am trying to get the error detection block working during configuration. I have followed this guide: accessing-error-detection-block-through-user-logic-cyclone-10-lp I have added the cyclone 10 lp components library and was able to instantiate this WYSIWYG atom: ------------------------------------------------------------------ -- cyclone10lp_crcblock parameterized megafunction component declaration -- Generated with 'mega_defn_creator' loader - do not edit ------------------------------------------------------------------ component cyclone10lp_crcblock generic ( lpm_hint : string := "UNUSED"; lpm_type : string := "cyclone10lp_crcblock"; oscillator_divider : natural := 1 ); port( clk : in std_logic := '0'; crcerror : out std_logic; ldsrc : in std_logic := '0'; regout : out std_logic; shiftnld : in std_logic := '0' ); end component; The crc block shows up in the technology map, and I am able to shift out the pre-calculated CRC and CRC result (depending on the ldsrc value) using the regout port. the CRC_ERROR pin is also working correctly. The timing is not working correctly. Regardless of the internal oscillator divisor setting, the time from INIT_DONE pin going high to CRC_ERROR pin going low is ~240 ms. I have tried changing the divisor setting in the quartus GUI, as well as in the generic map during instantiation. I was careful to make sure both matched, however even a divisor value of 256 does not change the timing at all. According to this CRC error detection timing table, the time should be between 9 ms and 4.51 s for the 10CL025 device on the dev kit (depending on oscillator divisor). Why am I not getting any time change when I change the oscillator divisor? I have tried in both Quartus 24.1 STD and 25.1 STDSolved44Views0likes4CommentsArria 10 Reconfiguration
Hello, I am working with an Arria 10 (10AS048) and using an external FPGA to manage configuration from a flash memory. When working with a non encrypted image, i am able to configure, then reconfigure, without issue. When i try to do the same thing with an encrypted image i have success on the initial configuration. Once i try to reconfigure I never get config_done. The A10 never pulls nStatus low to indicate a CRC error. When encryption is used is there something in the A10 that is stopping reconfiguration? Thanks24Views0likes1Comment10AX115H3F34E2SG, Laser marking
Dear INTEL/ALTERA Support Team, Good day. We previously purchased a batch of INTEL/ALTERA components from the authorized distributor ARROW and sold them to my client. Our client has raised concerns about the components having been re-marked. Model: 10AX115H3F34E2SG D/C: 2113, Lot Number: S848AK02TW, COO: Taiwan, Arrow Delivery ID: 011717919 We have received a statement regarding the product markings, which says: "De-mark/Re-mark is a qualified and controlled process within the manufacturing site. There is no impact on quality, reliability, and compliance with specifications on a de-marked/re-marked product." Attached please check our document. Could you please help verify the authenticity of this statement? Is it from Altera? We would greatly appreciate it if you could provide clarification to help address our client’s concerns. Hope to receive your feedback soon. Best regards, Carol Choi71Views0likes2CommentsAllow encrypted POF only
Hi! Can someone explain what this is security feature (Allow encrypted POF only) is supposed to do? In the description it says, "When enabled, devices accepts encrypted POF". However, this is not the case. After creating a .pof with "Allow encrypted POF only" and encryption, then loading this .pof + ekp file, everything after this first program/configure fails. This means you cannot program/configure/verify/blankcheck/examine with the same or different .pof/.ekp. The only solution is erase. But this feature should have allowed for encrypted pof to be programmed. Originally, I thought it would allow you to load a new .pof as long as you use the same key (.ekp). After experimenting with various cases, I cannot get pass the failure of reconfiguring the device. (CONFIG_DONE pin failed to go high in device 1. .... Operation Failed). The only solution is to erase. Which brings me back to the question of what is "Allow encrypted POF only" supposed to do? Can you provide procedures to get this feature to actual work? I am on Quartus Prime Standard Edition version 23.1 using a Max10 (m50) FPGA. Thank you!84Views0likes5Comments