Can Agilex 3 A3CY100BM16AE7S (AXC3000) use SDM cryptographic services?
Hello, I would like to confirm whether the SDM cryptographic services (user-mode access through the Mailbox Client IP) are supported on this device: Device: A3CY100BM16AE7S (Agilex 3 C-Series 100, M16A), Arrow AXC3000 board Tools: Quartus Prime Pro 26.1 build 110 Mailbox Client IP: Enable C-r-y-p-t-o Service = 1, C-r-y-p-t-o Memory Timeout = 10000, AXI manager connected to an on-chip RAM (confirmed in the compile log: intel_memory_initiator_endpoint with has_offload=1) Access: from fabric over Avalon-MM, no HPS What I observe (3 runs each, identical results, response FIFO empty after each command): - NOOP -> response header 0x00000000 (OK) - GET_IDCODE (0x10) -> header 0x00001000, data 0x4361B0DD (OK) - GET_CHIPID (0x12), GET_USERCODE (0x13), GET_TEMPERATURE (0x19), CONFIG_STATUS (0x04) -> all return the documented response lengths - open_crypto_service_session (0xA0) -> header 0x00001085 (error code 0x085, LENGTH=1), data word 0x000000FF - close_crypto_service_session, random_number_request, aes_crypt_request, get_digest_request, ecdsa sign/verify, ecdh_request -> header error code 0x085 (LENGTH=0) What the documentation says: - Agilex 3 C-Series Product Table (2026.02.11): specification code Y has C-r-y-p-t-o = No ("user mode access to the SDM hardened cryptographic IP"); codes U and W have C-r-y-p-t-o = Yes. - Security TRM: the error table of open_crypto_service_session lists both 0x0F (function not supported on the device) and 0x85 (command not allowed under the current security settings). - Security Overview for SDM-based devices, section 2.6, says the SDM C-r-y-p-t-o engines are made available to the FPGA design through the mailbox in user mode, without mentioning per-device restrictions. Questions: 1. Does A3CY100BM16AE7S (spec code Y) support SDM cryptographic services through the Mailbox Client IP? 2. If not, is 0x085 the expected response, or should it be 0x0F? 3. If the device is supposed to support them, what could make the SDM reject the command with 0x085 (security settings, provisioning, initialization)? 4. Is there any supported way to enable these services on this device? Thank you.Introducing the Altera Community AI Responder — Beta
Altera is introducing the AI Responder, an assistant built into the Altera Community to help provide faster, context-aware guidance for Altera product questions. It uses relevant public Altera documentation and Knowledge Database content, with coverage continuing to expand. The AI Responder may provide source references and can hand off complex or out-of-scope questions to an Altera subject-matter expert. As a beta feature, responses may contain errors or omissions, so please review the sources and verify technical guidance against official Altera documentation before implementation. If the response does not fully address your question, add more context and tag ai_responder to continue the discussion. We welcome your feedback as we improve the Community experience.
Quartus Programmer 21.1: JTAG Server Error Code 82 – Port 1309 Cannot Be Bound
Hello Altera Community, I am working on an FPGA project using a Cyclone IV FPGA development board and an Altera USB-Blaster. I am currently unable to program the FPGA because Quartus Programmer cannot access the JTAG server. System details: - OS: Windows 11 64-bit - Software: Quartus Programmer 21.1 - Installation path: C:\intelFPGA\21.1\qprogrammer - Programmer: Altera USB-Blaster - FPGA: Cyclone IV development board The USB-Blaster is detected by Windows Device Manager and the driver is installed. The USB-Blaster also powers on normally. However, Quartus Programmer gives: "Attempted to access JTAG server -- internal error code 82 occurred" When I run: jtagconfig I get: Error when scanning hardware - Server error Sometimes it also hangs at: Connecting to server(s) [...] I checked the JTAG server using: jtagserver --status It reports: Installed JTAG server is 'C:\intelFPGA\21.1\qprogrammer\bin64\jtagserver.exe' Server is stopped Remote clients are disabled I tried reinstalling the JTAG server: jtagserver --install jtagserver --start But the server immediately stops. I also tried: net start "Altera JTAG Server" The result was: The Altera JTAG Server service could not be started. The service did not report an error. NET HELPMSG 3534. I then ran: jtagserver.exe --foreground and received: Unable to bind changedetect socket: 10048 Can't bind to TCP port 1309 - exiting I checked the port using: netstat -ano | findstr 1309 and found that TCP port 1309 was being used/listened to by another process, for example PID 12888. I tried terminating the process using: taskkill /F /PID 12888 but Windows reported: ERROR: The process with PID 12888 could not be terminated. Reason: There is no running instance of the task. I also tried stopping the JTAG server, reinstalling it, and restarting it. In addition, I already tried the following: 1. Disabled PCI Express → Link State Power Management. 2. Disabled USB Root Hub power saving ("Allow the computer to turn off this device to save power"). 3. Stopped the Print Spooler service. 4. Closed Quartus/Programmer-related applications. 5. Reinstalled the JTAG Server. 6. Restarted the computer. 7. Tried starting the JTAG server manually. 8. Checked TCP port 1309 using netstat. The problem still remains. My main questions are: 1. Why is Quartus Programmer 21.1 unable to start the JTAG Server? 2. What is causing TCP port 1309 to remain occupied? 3. Is there a known issue with Quartus Programmer 21.1 and Windows 11? 4. Is there a recommended patch, driver, or newer Quartus Programmer version for this problem? 5. Is it possible to configure the JTAG server to use another TCP port? 6. What is the correct way to completely remove and reinstall the JTAG Server on Windows 11? 7. Is there anything else I should check before reinstalling Quartus Programmer? I would appreciate any guidance on how to get the JTAG Server running so that jtagconfig can detect my USB-Blaster and FPGA. Thank you.
Regarding the SDM Random Number Generator in Agilex 5 E-Series
Hi, Altera support team, <Overview> I have some questions about SDM Random Number Generator. But I cannot find any detailed information on that. I think it isn't public information. Could you answer below my questions? <Questions> 1. What is the entropy source? 2. How many bits of entropy are configurated? 3. Is the Random Number Generator configured as a combination of TRNG and DRBG? 4. Is it possible to provide documentation containing detailed information? <Note> We received these questions from a specific customer. So if possible, could you open a private session? BR, Wacky.
Updated .brd file for Stratix 10 GX dev kit
Referencing this post: EK-10M08E144 PCB .brd file corrupted | Altera Community - 302242 The .brd file that comes in the documentation at: https://www.altera.com/products/devkit/po-3028/stratix-10-gx-signal-integrity-development-kit-h-tile ...was done in Allegro, prior to version 16.6. The only available Allegro viewer gives an error because it was done prior to version 16.6, and you need the DB Doctor utility to update the file. The only way to get the DB Doctor utility is to install Allegro. If I had Allegro...I would not be installing the Allegro viewer. Altera: As mentioned in the post above (well over a year ago), it would make sense for you to update your files so customers can view the board of their $10K+ development board. How do we make that happen? Thanks!Cyclon 5 tampering protection bit
I have a cyclone V with an AS scheme. I have generated an key-file (ekp) with tampering protection bit set according to AN556 Then I open it in the programmer programmer and generate a jam-file now in the jam-file the procedure DO_KEY_SECURE is optional which means I have to enable that procedure manualy with "-e DO_KEY_SECURE" in the command, for example: quartus_jli -c <n> keys.jam -e DO_KEY_SECURE -a <action> is it possible to make this procedure non-optional so it will program the tampering bit by default when programming the key?
ModelSim-Intel FPGA Starter Edition 18.1 exits with code 211 when pressing Restart button
Hello, I am using ModelSim-Intel FPGA Starter Edition included with Quartus Prime Lite Edition 18.1. When I press the Restart button in the ModelSim GUI after running RTL simulation, ModelSim exits with the following message: "ModelSim is exiting with code 211. Check the transcript file for more information on the fatal error." Environment: - Quartus Prime Lite Edition 18.1 - ModelSim-Intel FPGA Starter Edition 18.1 - Windows PC - ModelSim path: C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem 確認したこと: - Quartus / ModelSim は再インストールされました。 - 環境変数とPATH設定を確認しました。 - 同じプロジェクトが別のPCで正しく再起動できる場合。 - このPCではGUIの再起動ボタンを押すと問題が発生します。 - PCにはTrend Micro Apex Oneがインストールされています。 - リアルタイムスキャンからIntel FPGA / ModelSimフォルダを除外した後、ModelSimは正しく動作しました。 質問: GUIの再起動ボタンを使う場合、ModelSim-Intel FPGA Starter Edition 18.1で既知の問題として、終了コード211はありますか? また、この問題はウイルス対策ソフトやエンドポイントセキュリティソフトに関係している可能性はありますか? この問題に対するおすすめの設定や回避策はありますか? ありがとうございます。
