Does the 1SG280LU2F50E2VG support bitfile encryption
I am attempting to encrypt and load an image to the 1SG280LU2F50E2VG on our Stratix 10 GX development kit following the instructions in AN 970: Intel® Stratix® 10 Security Tutorial. When I attempt to download the "root.qky" to the FPGA I see: Info(209060): Started Programmer operation at Thu Feb 12 18:01:59 2026 Info(18942): Configuring device index 1 Info(18943): Configuration succeeded at device index 1 Info(20091): Programming public key on device 1 Error(209012): Operation failed Info(209061): Ended Programmer operation at Thu Feb 12 18:02:02 2026 Is the FPGA on the development kit compatible with encryption?
Arria 10 Reconfiguration
Hello, I am working with an Arria 10 (10AS048) and using an external FPGA to manage configuration from a flash memory. When working with a non encrypted image, i am able to configure, then reconfigure, without issue. When i try to do the same thing with an encrypted image i have success on the initial configuration. Once i try to reconfigure I never get config_done. The A10 never pulls nStatus low to indicate a CRC error. When encryption is used is there something in the A10 that is stopping reconfiguration? Thanks
10AX115H3F34E2SG, Laser marking
Dear INTEL/ALTERA Support Team, Good day. We previously purchased a batch of INTEL/ALTERA components from the authorized distributor ARROW and sold them to my client. Our client has raised concerns about the components having been re-marked. Model: 10AX115H3F34E2SG D/C: 2113, Lot Number: S848AK02TW, COO: Taiwan, Arrow Delivery ID: 011717919 We have received a statement regarding the product markings, which says: "De-mark/Re-mark is a qualified and controlled process within the manufacturing site. There is no impact on quality, reliability, and compliance with specifications on a de-marked/re-marked product." Attached please check our document. Could you please help verify the authenticity of this statement? Is it from Altera? We would greatly appreciate it if you could provide clarification to help address our client’s concerns. Hope to receive your feedback soon. Best regards, Carol Choi
Allow encrypted POF only
Hi! Can someone explain what this is security feature (Allow encrypted POF only) is supposed to do? In the description it says, "When enabled, devices accepts encrypted POF". However, this is not the case. After creating a .pof with "Allow encrypted POF only" and encryption, then loading this .pof + ekp file, everything after this first program/configure fails. This means you cannot program/configure/verify/blankcheck/examine with the same or different .pof/.ekp. The only solution is erase. But this feature should have allowed for encrypted pof to be programmed. Originally, I thought it would allow you to load a new .pof as long as you use the same key (.ekp). After experimenting with various cases, I cannot get pass the failure of reconfiguring the device. (CONFIG_DONE pin failed to go high in device 1. .... Operation Failed). The only solution is to erase. Which brings me back to the question of what is "Allow encrypted POF only" supposed to do? Can you provide procedures to get this feature to actual work? I am on Quartus Prime Standard Edition version 23.1 using a Max10 (m50) FPGA. Thank you!The Verilog code was not actually programmed into the FPGA.
I have a question. I am using a 10M02SCM153C8G FPGA. I wrote a simple program, successfully programmed it onto the development board, and confirmed it produced the intended simple functionality. However, I've noticed that whenever I power cycle the evaluation board (by unplugging and replugging the USB cable), the board reverts to running the original sample code that was pre-loaded. This leads me to believe that although I performed the programming operation, the code was not actually programmed into the FPGA's non-volatile memory. Is there a specific option in the programming interface that I must select to ensure the code is permanently written to the FPGA's internal Configuration Flash Memory (CFM) block? As I recall, the MAX 10 series does not require an external SPI EEPROM for configuration, which I believe is correct. Does this also mean that if I do not select the correct programming option, the code is only loaded into the FPGA's volatile SRAM, and is therefore lost upon power-off?
Addressing PQC and CRA with Crypto-Agile Security in Agilex™ Devices
A look at today’s evolving security requirements affecting the semiconductor industry, including post-quantum cryptography (PQC) and the Cyber Resilience Act (CRA), and how Altera’s latest capabilities in Agilex™ 3 and Agilex™ 5 FPGAs and SoCs are helping to enable future-proof security functions today.
