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MartinMaa's avatar
MartinMaa
Icon for Occasional Contributor rankOccasional Contributor
26 days ago

The Verilog code was not actually programmed into the FPGA.

I have a question. I am using a 10M02SCM153C8G FPGA. I wrote a simple program, successfully programmed it onto the development board, and confirmed it produced the intended simple functionality. However, I've noticed that whenever I power cycle the evaluation board (by unplugging and replugging the USB cable), the board reverts to running the original sample code that was pre-loaded.

This leads me to believe that although I performed the programming operation, the code was not actually programmed into the FPGA's non-volatile memory. Is there a specific option in the programming interface that I must select to ensure the code is permanently written to the FPGA's internal Configuration Flash Memory (CFM) block?

As I recall, the MAX 10 series does not require an external SPI EEPROM for configuration, which I believe is correct. Does this also mean that if I do not select the correct programming option, the code is only loaded into the FPGA's volatile SRAM, and is therefore lost upon power-off?

 

 

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5 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    26 days ago

    Hi,

    as you say, need to select the correct programming option. In Quartus Programmer, load .pof instead of .sof file. For details, refer to MAX 10 Configuration User Guide, paragraph 3.3.3.

    Regards Frank

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    25 days ago

    FYI, link to the MAX 10 docs: https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/max-10-support.html

  • MartinMaa's avatar
    MartinMaa
    Icon for Occasional Contributor rankOccasional Contributor
    26 days ago

    Hi Frank,

    I have another question for you. I need to know how many embedded M9K memory blocks are available in the 10M02SCM153C8G FPGA.

    I plan to use this FPGA to implement an 8K x 9 SYNCFIFO using an IP core. However, I have been unable to locate this specific information. I've consulted an AI, which provided conflicting responses on whether this implementation is feasible.

    Could you please let me know in which chapter of the documentation I can find the data on the number of M9K memory blocks? Alternatively, would you be able to confirm if the device has sufficient resources for my application?

    Thank you.

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    26 days ago

    Hi Martin,
    the memory resources info is in Intel® MAX® 10 FPGA Device Overview document. It tells 108 kb for 10M02 = 12 9k blocks. If your application is 8kx9, you'll need 8 of the available 12 blocks.

    You can also consult MAX10 Device Handbook if the intended memory configuration is supported. You see that 1024x9k is avavilable for true dual port, e.g. domain crossing FIFO. See  paragraph 2.4. Intel MAX 10 Embedded Memory Configurations

    Sucessful implementation in Quartus is of course the ultimate validation.

    Regards
    Frank