The Verilog code was not actually programmed into the FPGA.

Hi Martin,
the memory resources info is in Intel® MAX® 10 FPGA Device Overview document. It tells 108 kb for 10M02 = 12 9k blocks. If your application is 8kx9, you'll need 8 of the available 12 blocks.

You can also consult MAX10 Device Handbook if the intended memory configuration is supported. You see that 1024x9k is avavilable for true dual port, e.g. domain crossing FIFO. See  paragraph 2.4. Intel MAX 10 Embedded Memory Configurations

Sucessful implementation in Quartus is of course the ultimate validation.

Regards
Frank