Clarification on Arria 10 Design Security Features
We're working on securing the IP using design security features available in the Arria 10 FPGA. We went through the AN556 multiple times, but still some aspects are not clear to us. We've successfully configured the non-volatile key into the FPGA, but we did not set the tamper protection in the EKP file. Is it still possible to enable it on this device? Is the tamper protection set per key type (volatile/non-volatile)? Or is it effective for both volatile and non-volatile keys? Let's say that EKP and the encrypted bitstream leaked. Is it possible to extract the key from the EKP file to decrypt the bitstream? Is there a possibility to check from the FPGA fabric whether the non-volatile key was configured or not? I mean, e.g. is it possible to instantiate the Internal JTAG interface/WYSIWYG atom and execute the KEY_VERIFY instruction? If tamper protection is enabled, is it still possible to configure the FPGA with the SOF file? If JTAG secure mode is enabled, is it still possible to configure the FPGA using JTAG? That's a lot of questions. Thanks in advance. DamianVerifying Cyclone V FPGA functionality using different FPGA flash devices (Intel / Micron).
We have two boards using the same Cyclone V FPGA, the only difference between the two boards is the serial flash devices for the FPGA, being the Micron or Intel flash device. We need to verify each of these flash device’s rpd file, to verify the FPGA functionality will be identical. However the rpd files are slightly different, from bytes 128 to 298 (ie: 170 bytes), as just below, and noting before and after this section it looks to be only padding, ie: FFs: So the question is, when validating the FPGA flash device’s rpd file (in software), is there a certain amount or section of initial bytes we can skip, though still ensure the exact same functionality of the FPGA itself ? Ie: I assume this first section of the rpd file does not affect the FPGA functionality (once flashed) ? Also would anyone know what is in the first section of the rpd file up to about byte 298 in this case ? Also noting I’m a software engineer with limited knowledge of the hardware, Thanks, Glenn
Why does Partial Reconfiguration (PR) via HPS fail only when using encrypted PR bitstreams?
Description Partial Reconfiguration (PR) via HPS fails only when using encrypted PR bitstreams. This failure only happened on encrypted PR bitstream and not base bitstream. Error message display: root@agilex:~# mv /tmp/pr.rbf /lib/firmware/persona0.rbf root@agilex:~# /usr/bin/dtbt -a /lib/firmware/agilex7_pr_fpga_static_region.dtbo Applying dtbo: /lib/firmware/agilex7_pr_fpga_static_region.dtbo [ 251.625026] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/ranges [ 251.638872] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/external-fpga-config [ 251.649792] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/clocks [ 251.659426] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/clock-names [ 251.669543] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clk_0 [ 251.679105] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/freeze_controller_0 [ 251.693803] of-fpga-region fpga-region:fpga_pr_region0: FPGA Region probed root@agilex:~# /usr/bin/dtbt -a /lib/firmware/agilex7_pr_persona0.dtbo Applying dtbo: /lib/firmware/agilex7_pr_persona0.dtbo [ 262.265981] fpga_manager fpga0: writing persona0.rbf to Stratix10 SOC FPGA Manager [ 267.497950] Stratix10 SoC FPGA manager firmware:svc:fpga-mgr: timeout waiting for svc layer buffers Resolution This problem is scheduled to be fixed in a future release of Quartus® Prime Pro Edition software.
Inquiry regarding purchasing FPGA licenses
We are looking to purchase Intel FPGA software licenses for our company, specifically: * Intel NCO MegaCore IP license * Intel Quartus Prime Standard Edition license Can someone please help with the supplier on where we can do this transaction ? Thank you so much!
Does the 1SG280LU2F50E2VG support bitfile encryption
I am attempting to encrypt and load an image to the 1SG280LU2F50E2VG on our Stratix 10 GX development kit following the instructions in AN 970: Intel® Stratix® 10 Security Tutorial. When I attempt to download the "root.qky" to the FPGA I see: Info(209060): Started Programmer operation at Thu Feb 12 18:01:59 2026 Info(18942): Configuring device index 1 Info(18943): Configuration succeeded at device index 1 Info(20091): Programming public key on device 1 Error(209012): Operation failed Info(209061): Ended Programmer operation at Thu Feb 12 18:02:02 2026 Is the FPGA on the development kit compatible with encryption?
Arria 10 Reconfiguration
Hello, I am working with an Arria 10 (10AS048) and using an external FPGA to manage configuration from a flash memory. When working with a non encrypted image, i am able to configure, then reconfigure, without issue. When i try to do the same thing with an encrypted image i have success on the initial configuration. Once i try to reconfigure I never get config_done. The A10 never pulls nStatus low to indicate a CRC error. When encryption is used is there something in the A10 that is stopping reconfiguration? Thanks
