Why does Partial Reconfiguration (PR) via HPS fail only when using encrypted PR bitstreams?

Description

Partial Reconfiguration (PR) via HPS fails only when using encrypted PR bitstreams. This failure only happened on encrypted PR bitstream and not base bitstream.

Error message display:
root@agilex:~# mv /tmp/pr.rbf /lib/firmware/persona0.rbf
root@agilex:~# /usr/bin/dtbt -a /lib/firmware/agilex7_pr_fpga_static_region.dtbo
Applying dtbo: /lib/firmware/agilex7_pr_fpga_static_region.dtbo
[  251.625026] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/ranges
[  251.638872] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/external-fpga-config
[  251.649792] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/clocks
[  251.659426] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/clock-names
[  251.669543] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clk_0
[  251.679105] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/freeze_controller_0
[  251.693803] of-fpga-region fpga-region:fpga_pr_region0: FPGA Region probed
root@agilex:~# /usr/bin/dtbt -a /lib/firmware/agilex7_pr_persona0.dtbo
Applying dtbo: /lib/firmware/agilex7_pr_persona0.dtbo
[  262.265981] fpga_manager fpga0: writing persona0.rbf to Stratix10 SOC FPGA Manager
[  267.497950] Stratix10 SoC FPGA manager firmware:svc:fpga-mgr: timeout waiting for svc layer buffers

Resolution

This problem is scheduled to be fixed in a future release of Quartus® Prime Pro Edition software.