Updated .brd file for Stratix 10 GX dev kit
Referencing this post: EK-10M08E144 PCB .brd file corrupted | Altera Community - 302242 The .brd file that comes in the documentation at: https://www.altera.com/products/devkit/po-3028/stratix-10-gx-signal-integrity-development-kit-h-tile ...was done in Allegro, prior to version 16.6. The only available Allegro viewer gives an error because it was done prior to version 16.6, and you need the DB Doctor utility to update the file. The only way to get the DB Doctor utility is to install Allegro. If I had Allegro...I would not be installing the Allegro viewer. Altera: As mentioned in the post above (well over a year ago), it would make sense for you to update your files so customers can view the board of their $10K+ development board. How do we make that happen? Thanks!
Cyclon 5 tampering protection bit
I have a cyclone V with an AS scheme. I have generated an key-file (ekp) with tampering protection bit set according to AN556 Then I open it in the programmer programmer and generate a jam-file now in the jam-file the procedure DO_KEY_SECURE is optional which means I have to enable that procedure manualy with "-e DO_KEY_SECURE" in the command, for example: quartus_jli -c <n> keys.jam -e DO_KEY_SECURE -a <action> is it possible to make this procedure non-optional so it will program the tampering bit by default when programming the key?Quartus Programmer 21.1: JTAG Server Error Code 82 – Port 1309 Cannot Be Bound
Hello Altera Community, I am working on an FPGA project using a Cyclone IV FPGA development board and an Altera USB-Blaster. I am currently unable to program the FPGA because Quartus Programmer cannot access the JTAG server. System details: - OS: Windows 11 64-bit - Software: Quartus Programmer 21.1 - Installation path: C:\intelFPGA\21.1\qprogrammer - Programmer: Altera USB-Blaster - FPGA: Cyclone IV development board The USB-Blaster is detected by Windows Device Manager and the driver is installed. The USB-Blaster also powers on normally. However, Quartus Programmer gives: "Attempted to access JTAG server -- internal error code 82 occurred" When I run: jtagconfig I get: Error when scanning hardware - Server error Sometimes it also hangs at: Connecting to server(s) [...] I checked the JTAG server using: jtagserver --status It reports: Installed JTAG server is 'C:\intelFPGA\21.1\qprogrammer\bin64\jtagserver.exe' Server is stopped Remote clients are disabled I tried reinstalling the JTAG server: jtagserver --install jtagserver --start But the server immediately stops. I also tried: net start "Altera JTAG Server" The result was: The Altera JTAG Server service could not be started. The service did not report an error. NET HELPMSG 3534. I then ran: jtagserver.exe --foreground and received: Unable to bind changedetect socket: 10048 Can't bind to TCP port 1309 - exiting I checked the port using: netstat -ano | findstr 1309 and found that TCP port 1309 was being used/listened to by another process, for example PID 12888. I tried terminating the process using: taskkill /F /PID 12888 but Windows reported: ERROR: The process with PID 12888 could not be terminated. Reason: There is no running instance of the task. I also tried stopping the JTAG server, reinstalling it, and restarting it. In addition, I already tried the following: 1. Disabled PCI Express → Link State Power Management. 2. Disabled USB Root Hub power saving ("Allow the computer to turn off this device to save power"). 3. Stopped the Print Spooler service. 4. Closed Quartus/Programmer-related applications. 5. Reinstalled the JTAG Server. 6. Restarted the computer. 7. Tried starting the JTAG server manually. 8. Checked TCP port 1309 using netstat. The problem still remains. My main questions are: 1. Why is Quartus Programmer 21.1 unable to start the JTAG Server? 2. What is causing TCP port 1309 to remain occupied? 3. Is there a known issue with Quartus Programmer 21.1 and Windows 11? 4. Is there a recommended patch, driver, or newer Quartus Programmer version for this problem? 5. Is it possible to configure the JTAG server to use another TCP port? 6. What is the correct way to completely remove and reinstall the JTAG Server on Windows 11? 7. Is there anything else I should check before reinstalling Quartus Programmer? I would appreciate any guidance on how to get the JTAG Server running so that jtagconfig can detect my USB-Blaster and FPGA. Thank you.
ModelSim-Intel FPGA Starter Edition 18.1 exits with code 211 when pressing Restart button
Hello, I am using ModelSim-Intel FPGA Starter Edition included with Quartus Prime Lite Edition 18.1. When I press the Restart button in the ModelSim GUI after running RTL simulation, ModelSim exits with the following message: "ModelSim is exiting with code 211. Check the transcript file for more information on the fatal error." Environment: - Quartus Prime Lite Edition 18.1 - ModelSim-Intel FPGA Starter Edition 18.1 - Windows PC - ModelSim path: C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem 確認したこと: - Quartus / ModelSim は再インストールされました。 - 環境変数とPATH設定を確認しました。 - 同じプロジェクトが別のPCで正しく再起動できる場合。 - このPCではGUIの再起動ボタンを押すと問題が発生します。 - PCにはTrend Micro Apex Oneがインストールされています。 - リアルタイムスキャンからIntel FPGA / ModelSimフォルダを除外した後、ModelSimは正しく動作しました。 質問: GUIの再起動ボタンを使う場合、ModelSim-Intel FPGA Starter Edition 18.1で既知の問題として、終了コード211はありますか? また、この問題はウイルス対策ソフトやエンドポイントセキュリティソフトに関係している可能性はありますか? この問題に対するおすすめの設定や回避策はありますか? ありがとうございます。
Arria 10SX current drawn during non-volatile key programming
Hi, we are using in our design an Arria10 SX (precisely the 10AS027E4F29E3SG) device. The design had been successfully manufactured for approx. 100 units. For one customer we decided to use design security and started to program a non-volatile key into the FPGA and use encrypted bitstreams later on. It turned out that appox every tenth unit failed now because the power manager found either an excessive current on the global supply or the VCCPT (1.8V) was degraded while programming the non-volatile key. Note, the supply driving the VCCPT had been designed to provide +70% current as calculated by the Quartus power analyzer (by the way it did not help that this support had been removed for Arria 10 from Quartus Pro, I did not check which versions actually support it, 18.1 works, 23.2 fails). Thus there is a reserve of approx 550mA at the supply. It obviously comes to its limits during the non-volatie key programming. I searched (again) for a specification in the Altera Arria 10 documentation (mainly datasheet, handbook and AN556) which current is drawn on which supply while programming the non-volatile key. I did not find any information on that. Can you please point me to the documentation where I can find this specification or can you provide me the numbers? Even an estimate will help. Thank you! Gerhard
URGENT SUPPORT FOR FMD DATA COLLECTION
Hi Team, I am Siddesh Chavan from the NetApp Component Engineering Team. As part of our component compliance review and documentation update process, we are reviewing the Lotes Co. Ltd part. We kindly request your support in providing the information requested for the components listed in the attached file. Please acknowledge receipt of this email and confirm whether you can provide the requested details. Your support will help us keep our records accurate and up to date. Thank you for your support and cooperation. We look forward to your response. Regards, Siddesh Chavan
Licence in Altera 2 Complete Design Suite version 13.0 SP1 For cyclone 1
"I am using Quartus II 13.0 Subscription Edition to compile code for a Cyclone I device (EP1C3T100C8). While the build compiles successfully, the software does not generate the .sof file needed to create a .jic file. Since this device family might have limited support, does anyone know how to enable or generate the .sof file in this version?"
Agilex 3: VCCBAT pin for the battery-backed key storage.
Hello Everyone, I’ve been looking into Agilex 3 devices and noticed that the VCCBAT pin for the battery-backed key storage is missing from the pin lists. We've checked the pinouts for the A3CZ, A3CV, A3CW, and A3CY device families in both the 100 and 135 package sizes, and none of them include a VCCBAT pin. At the same time, when reviewing the power tree in the Agilex 3 PCB Design Guidelines (https://docs.altera.com/r/docs/853726/current/pcb-design-guidelines/power-tree), the VCCBAT supply is shown in the diagram and described in the accompanying table, similar to what was done for Agilex 5 devices. Does this mean that Agilex 3 devices do not support storing an encryption key in BBRAM and only support a permanent key stored in fuses? Or are we looking at the wrong device variants? Are there specific Agilex 3 devices (or package options) with additional security features that support a battery-backed key and therefore include a VCCBAT pin? Thanks in advance, Tomasz
