Agilex 3: VCCBAT pin for the battery-backed key storage.
Hello Everyone, I’ve been looking into Agilex 3 devices and noticed that the VCCBAT pin for the battery-backed key storage is missing from the pin lists. We've checked the pinouts for the A3CZ, A3CV, A3CW, and A3CY device families in both the 100 and 135 package sizes, and none of them include a VCCBAT pin. At the same time, when reviewing the power tree in the Agilex 3 PCB Design Guidelines (https://docs.altera.com/r/docs/853726/current/pcb-design-guidelines/power-tree), the VCCBAT supply is shown in the diagram and described in the accompanying table, similar to what was done for Agilex 5 devices. Does this mean that Agilex 3 devices do not support storing an encryption key in BBRAM and only support a permanent key stored in fuses? Or are we looking at the wrong device variants? Are there specific Agilex 3 devices (or package options) with additional security features that support a battery-backed key and therefore include a VCCBAT pin? Thanks in advance, Tomasz
Licence in Altera 2 Complete Design Suite version 13.0 SP1 For cyclone 1
"I am using Quartus II 13.0 Subscription Edition to compile code for a Cyclone I device (EP1C3T100C8). While the build compiles successfully, the software does not generate the .sof file needed to create a .jic file. Since this device family might have limited support, does anyone know how to enable or generate the .sof file in this version?"
URGENT SUPPORT FOR FMD DATA COLLECTION
Hi Team, I am Siddesh Chavan from the NetApp Component Engineering Team. As part of our component compliance review and documentation update process, we are reviewing the Lotes Co. Ltd part. We kindly request your support in providing the information requested for the components listed in the attached file. Please acknowledge receipt of this email and confirm whether you can provide the requested details. Your support will help us keep our records accurate and up to date. Thank you for your support and cooperation. We look forward to your response. Regards, Siddesh Chavan
ModelSim-Intel FPGA Starter Edition 18.1 exits with code 211 when pressing Restart button
Hello, I am using ModelSim-Intel FPGA Starter Edition included with Quartus Prime Lite Edition 18.1. When I press the Restart button in the ModelSim GUI after running RTL simulation, ModelSim exits with the following message: "ModelSim is exiting with code 211. Check the transcript file for more information on the fatal error." Environment: - Quartus Prime Lite Edition 18.1 - ModelSim-Intel FPGA Starter Edition 18.1 - Windows PC - ModelSim path: C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem 確認したこと: - Quartus / ModelSim は再インストールされました。 - 環境変数とPATH設定を確認しました。 - 同じプロジェクトが別のPCで正しく再起動できる場合。 - このPCではGUIの再起動ボタンを押すと問題が発生します。 - PCにはTrend Micro Apex Oneがインストールされています。 - リアルタイムスキャンからIntel FPGA / ModelSimフォルダを除外した後、ModelSimは正しく動作しました。 質問: GUIの再起動ボタンを使う場合、ModelSim-Intel FPGA Starter Edition 18.1で既知の問題として、終了コード211はありますか? また、この問題はウイルス対策ソフトやエンドポイントセキュリティソフトに関係している可能性はありますか? この問題に対するおすすめの設定や回避策はありますか? ありがとうございます。Clarification on Agilex 3 W vs Y Device Variants and Security Feature Mapping
Hi support team, I hope you are doing well. I am currently evaluating Agilex™ 3 devices for a design and would like to clarify the detailed differences between the W and Y device variants, particularly regarding their security capabilities. After reviewing several official documents, I found that the description is not entirely aligned, and I would appreciate your clarification with references to the official definitions. I have mainly referred to the following documents: Security Overview for SDM-Based FPGA Devices Agilex™ 3 FPGAs and SoCs C‑Series Product Table Agilex™ 3 FPGAs and SoCs Device Data Sheet Questions and points needing clarification In the Agilex 3 product table, the W/Y/Z variants are differentiated by a “C-r-y-p-t-o” field. Could you please clarify: What exactly is included in “C-r-y-p-t-o”? Does this explicitly include: ECDSA authentication SHA‑384 integrity verification Secure boot / authenticated configuration Or does it also include lower-level cryptographic primitives (AES, SHA engines, etc.)? 2, In the Security Overview document, it states that: SDM contains cryptographic engines (AES, SHA, ECC) and key management hardware, and these can also be accessed by user logic. From this description, it appears that: Cryptographic primitives exist in the platform (even for Y devices) So the question is: Are cryptographic engines available in both Y and W variants? If yes, is the difference that: W enables secure system-level usage (authentication / secure boot) while Y only exposes these engines for user application use? 3,From the product table and security overview: PUF SPDM attestation Physical anti‑tamper monitoring appear to be available beyond just W variants. Could you confirm: Are these features available on both Y and W devices? If so, what is the functional difference in how they are used? For example: Monitoring vs enforcement Reporting vs blocking 4,In the document: Security Overview for SDM-Based FPGA Devices Table 1 seems to indicate that Agilex 3 devices generally support both encryption and authentication, without distinguishing between W and Y variants. This creates confusion when compared with the product table. Could you please clarify: Is Table 1 describing platform-level capability (architecture-based) rather than specific device configurations? And is the correct interpretation that: Only W variants enable full cryptographic security flows (e.g. authenticated configuration / root-of-trust) while Y variants provide only partial or application-level capabilities? My design really care the security and low power consumption rather than performance or high speed tranceivers. we only nee 30KLE, 300Kbit RAM, 2 PLL,200GPIO, no tranceiver ,no high speed needed so smaller density A3CY025BB18AI7S of Agilex3 might suitable but security W is not available in that small density, so I would like to know if we choose Code Y then what security features is missing from W. Regard JL
Verifying Cyclone V FPGA functionality using different FPGA flash devices (Intel / Micron).
We have two boards using the same Cyclone V FPGA, the only difference between the two boards is the serial flash devices for the FPGA, being the Micron or Intel flash device. We need to verify each of these flash device’s rpd file, to verify the FPGA functionality will be identical. However the rpd files are slightly different, from bytes 128 to 298 (ie: 170 bytes), as just below, and noting before and after this section it looks to be only padding, ie: FFs: So the question is, when validating the FPGA flash device’s rpd file (in software), is there a certain amount or section of initial bytes we can skip, though still ensure the exact same functionality of the FPGA itself ? Ie: I assume this first section of the rpd file does not affect the FPGA functionality (once flashed) ? Also would anyone know what is in the first section of the rpd file up to about byte 298 in this case ? Also noting I’m a software engineer with limited knowledge of the hardware, Thanks, Glenn
