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JScho6's avatar
JScho6
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Detailed re-configurable PLL data description for Cyclone 10?

Hi, we're designing a scan rate converter and scaler with an Intel Cyclone 10 FPGA. The output pixel clock shall be configurable, and we've solved a bit of the puzzle, but not all of it yet. As the...
JScho6's avatar
JScho6
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Checking complete: It is the exact same info as in the datasheet. So no detailed bit order (which is no problem for us anymore as we got that from a different document combined with reverse-engineering the Quartus output).

No info how to calculate the charge pump or loop filter to get a specific bandwidth. So yet another *BUMP* with the kind request from a paying customer for proper documentation.

Just a hint: That order for 84 boxes=9996 pcs. 10CL010 is mine (placed through Arrow Germany). I really don't want to play around with "black box values" any longer, as we prefer engineering over tinkering here.

greetings,

Jens