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JScho6
Occasional Contributor
Occasional ContributorDetailed re-configurable PLL data description for Cyclone 10?
Hi, we're designing a scan rate converter and scaler with an Intel Cyclone 10 FPGA. The output pixel clock shall be configurable, and we've solved a bit of the puzzle, but not all of it yet. As the...
JScho6Occasional Contributor
Occasional Contributor*BUMP*
Another week has passed, and still no documentation, not even a comment about the document errors I have reported here. Still trying to find that guy who has the knowledge?
kind regards,
Jens
