Detailed re-configurable PLL data description for Cyclone 10?

Hi Jens,

I apologize that the responses here in the forum does not satisfy to what you are looking/requiring. We will channel your input and feedback to the internal/engineering team responsible on this IP for them to consider future documentation enhancement. You are correct there are errors in the document and what we can do is to submit the request to the internal team to take the appropriate action accordingly.

Nevertheless, regarding on the details information that your are questing, unless the engineering team can release/provide the information on the correct multiplication and divisor combination meeting the legal range/limits of the PLL/FPLL IP algorithm then we don't have the direct way to generate desire output clock without trial and error. The information that you are requesting are not available for public use since this is part of the IP and device proprietary.

For other PLL issues (Cyclone 10 PLL stability issue with low reference frequencies 8Mhz) than the original question posted here, I suggest that you can submit another thread. We will find and assign an engineer to help to look into it. Otherwise you may consult with your local distributor, Arrow if you still require further support on this topic.

Regards,

Nooraini